【正文】 utput sine wave is 2n /m, and the output frequency (fDDS) and the frequency resolution (fres) are given by the following formulas： m fclk 2n n fres= fclk/ 2 fDDS= For n = 32 and having a clock frequency of fclk = 33 MHz, the frequency resolution is mHz. If n is increased to 48, with the same clock frequency, a resolution of 120 nHz is possible. 3 The proposed frequency measurement technique The idea that led to our present design came from the extremely high frequency resolution of the DDS devices and is enforced by the noise immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a closed loop and is forced progressively to produce an output with a frequency equal to the unknown input . A rule of thumb in the DDS systems is that the maximum acceptable synthesized frequency is about 25% of the clock frequency (well below the Nyquist limit). According to this, our prototype that uses a 33 MHz clock would effectively count up to 8 MHz. Looking at the GaAs products, we can see that recently available DDS devises can operate at clock frequencies up to the extent of 400 MHz. Therefore, by the present method, frequency counters working up to 100 MHz can be designed. The resolution will depend on the number of FSW bits and the clock frequency. The clock frequency fclk of the DDS is very critical because as it decreases, the resolution of the proposed method (defined as fclk/ 2n ) bees finer . it improves. The impact of the clock frequency decrease is the subsequent decrease of its maximum output frequency that limits the counter39。s maximum count. The major blocks have been shown . Among them are the Frequency Comparator and the DDS. To overe some disadvantages of the specific frequency parator a correction stage has been incorporated. This stage is also used for the measurement extraction in order to display the correct reading. Operation of the circuit The circuit operates in such a way that at the beginning of a new measurement the DDS output frequency would be controlled in a successive approximation way. The initial DDS frequency would be half of it39。s maximum. In addition, the frequency step of the approximation would equal the 1/4 of the DDS maximum frequency. On every approximation the frequency step is divided by two and added or subtracted to the FSW of the DDS, depending on the output of the Frequency Comparator. The approximation procedure stops when the step size decreases to one. After that, an up/down counter substitutes the approximation mechanism. The digital FSW, after the appropriate correction and decoding, is presented in an output device . an LCD display or any other suitable means. Alternatively, it can be digitally recorded or it can be read by a puter. As conclusion of this initial approach we could say that the proposed method is based on a Digital Controlled Synthesizer which is forced to produce a frequency almost equal to the unknown one. Frequency parison The frequency parator seems to be the most critical stage of the design. The implementation is based on a modified phase/frequency parator proposed by Philips in the 74HC4046 PLL device. It consists primarily of two binary counters, counting up to two and an RS flipflop. The function of the frequency parator is based on the principle that the lower frequency, . larger period, includes (embraces) at least one or more full periods of the higher frequency (smaller period). This means that two or more rising edges of the higher frequency waveform are included within the lower frequency period. Considering the above, the circuit operates as follows: When the first counter (1) encounters two rising edges of the unknown frequency in one period of the DDS, it sets the output of the RS flipflop. The logic 1 of the RS flipflop acting at the U/D control input of the Up/Down counter forces the DDS to rise its output frequency. On the contrary, when the second counter (2) counts two rising edges of the DDS output within a period of the unknown frequency it resets the RS flipflop39。s output. This action decreases the frequency of the DDS. At a first glance one could think that the synt