【正文】 end if。 end if。 end if。 q=tmp。 end process。 end delta_arc。LIBRARY ieee。 正弦波模塊use 。use 。entity delta is port(clk,reset:in std_logic。 q:out std_logic_vector(7 downto 0))。end delta。architecture delta_arc of delta isbegin process(clk,reset) variable tmp:std_logic_vector(7 downto 0)。 variable a:std_logic。 begin if reset=39。039。 then tmp:=00000000。 elsif clk39。event and clk=39。139。 then if a=39。039。then if tmp=11111000then tmp:=11111111。 a:=39。139。 else tmp:=tmp+8。 end if。 else if tmp=00000111then tmp:=00000000。 a:=39。039。 else tmp:=tmp8。 end if。 end if。 end if。 q=tmp。 end process。 end delta_arc。LIBRARY ieee?？刂颇Kuse 。use 。entity chpro31 is port(dlt,sqr,sin:in std_logic。 dlta,sqra,sina:in std_logic_vector(7 downto 0)。 q:out std_logic_vector(7 downto 0))。end chpro31。architecture ch_arc of chpro31 isbegin process(dlt,dlta,sqr,sqra,sin,sina) variable tmp:std_logic_vector(2 downto 0)。 variable a,b:std_logic_vector(9 downto 0)。 variable c,d,e:std_logic_vector(9 downto 0)。 begin tmp:=dltamp。sqramp。sin。 case tmp is when 100=q=dlta。 when 010=q=sqra。 when 001=q=sina。 when 110=a:=00amp。dlta+sqra。 q=a(8 downto 1)。 when 101=a:=00amp。dlta+sina。 q=a(8 downto 1)。 when 011=a:=00amp。sqra+sina。 q=a(8 downto 1)。 when 111=a:=00amp。dlta+sqra。 b:=a+sina。 c:=00amp。b(9 downto 2)。 d:=0000amp。a(9 downto 4)。 e:=000000amp。a(9 downto 6)。 a:=c+d。 b:=a+e。 q=b(7 downto 0)。 when others=null。 end case。 end process。end ch_arc。附錄2 元件介紹1 DAC0832DAC0832 是一種相當(dāng)普遍且成本較低的數(shù)/模轉(zhuǎn)換器，該器件是一個(gè)8位D/A轉(zhuǎn)換器，其轉(zhuǎn)換時(shí)間為1s，工作電壓為+5V～+15V，基準(zhǔn)電壓為177。10V，它將一個(gè)8位的二進(jìn)制數(shù)轉(zhuǎn)換成模擬電壓，可產(chǎn)生256種不同的電壓值，由于其內(nèi)部有兩個(gè)8位寄存器和一個(gè)8位D/A轉(zhuǎn)換器，故可進(jìn)行兩級(jí)緩沖操作，使操作有很大的靈活性(本設(shè)計(jì)中采用的是單緩沖方式)．DAC0832具有以下主要特性：①滿足TTL電平規(guī)范的邏輯輸入；②分辨率為8位； ③建立時(shí)間為1us；④功耗20mw；⑤是電流型輸出型D/A轉(zhuǎn)換器，在應(yīng)用時(shí)外接運(yùn)放使之成為電壓型輸出。DAC0832的片選地址為7FFFH，當(dāng)P27有效時(shí)，若P0口向其送的數(shù)據(jù)為00H，則U 的輸出電壓為0V；若P0口向其送的數(shù)據(jù)為0FFH時(shí)，則的輸出電壓為5V．故當(dāng)輸出電壓為0V時(shí)，Vo：5V．當(dāng)輸出電壓為5V時(shí)，可得：Vo =+5V，所以輸出波形的電壓變化范圍為5V ～+5V．連接硬件電路時(shí)將兩級(jí)寄存器的控制信號(hào)并接輸入數(shù)據(jù)，在控制信號(hào)作用下直接送入DAC寄存器中。經(jīng)D/A轉(zhuǎn)換和幅度控制，再濾波即可得到波形。圖1 DAC0832內(nèi)部結(jié)構(gòu)如圖所示圖2 DAC08322 LM324LM324四運(yùn)放是美國national公司的產(chǎn)品。LM324是四運(yùn)放集成電路,它采用14腳雙列直插塑料封裝。它的內(nèi)部包含四組形式完全相同的運(yùn)算放大器, 除電源共用外,四組運(yùn)放相互獨(dú)立。每一組運(yùn)算放大器可用圖1所示的符號(hào)來表示,它有5個(gè)引出腳,其中“+”、“”為兩個(gè)信號(hào)輸入端,“V+”、“V”為正、負(fù)電源端,“Vo”為輸出端。兩個(gè)信號(hào)輸入端中,Vi（）為反相輸入端,表示運(yùn)放輸出端Vo的信號(hào)與該輸入端的位相反。Vi+（+）為同相輸入端,表示運(yùn)放輸出端Vo的信號(hào)與該輸入端的相位相同。由于LM324四運(yùn)放電路具有電源電壓范圍寬,靜態(tài)功耗小,可單電源使用,價(jià)格低廉等優(yōu)點(diǎn),因此被廣泛應(yīng)用在各種電路中。 在本系統(tǒng)中，LM324被作為放大器和濾波器來使用。它可以選出各個(gè)不同頻段的信號(hào),指示出信號(hào)幅度的大小，對信號(hào)進(jìn)行放大后再輸出，提供給使用者需要的波形信號(hào)。圖3 LM324管腳圖3 PM7128SLC8415芯片 EPM7128S8415是CPLD芯片，有128個(gè)宏單元、2500個(gè)等效邏輯門、15ns的速度、PLCC84封裝形式。除電源引腳、地線引腳、全局控制引腳和JTAG引腳外，共提供了64個(gè)可用I/O腳，這些引腳可以任意配置為輸入、輸出和雙向方式。該器件的特點(diǎn)如下:l 是 一 種高性能的CM0SE EPROM器件。l 器 件 可通過JTAG接口實(shí)現(xiàn)在線編程。l 內(nèi) 置JTAG BST電路。l 可 編 程宏單元觸發(fā)器具有專用清除、置位、時(shí)鐘和時(shí)鐘使能控制。l 可 配 置的擴(kuò)展乘積項(xiàng)分配，允許向每個(gè)宏單元提供多達(dá)32個(gè)乘積項(xiàng)。 圖4EPM7128SLC8415 附錄3電路原理圖附錄4 英文資料及譯文1英文資料(From DIGITAL DESIGN principles amp。 practices ,John F. Wakerly)Language OverviewWhat is VHDL?VHDL is a programming language that has been designed and optimized for describing the behavior of digital systems.VHDL has many features appropriate for describing the behavior of electronic ponents ranging from simple logic gates to plete microprocessors and custom chips. Features of VHDL allow electrical aspects of circuit behavior (such as rise and fall times of signals, delays through gates, and functional operation) to be precisely described. The resulting VHDL simulation models can then be used as building blocks in larger circuits (using schematics, block diagrams or systemlevel VHDL descriptions) for the purpose of simulation.VHDL is also a generalpurpose programming language: just as highlevel programming languages allow plex design concepts to be expressed as puter programs, VHDL allows the behavior of plex electronic circuits to be captured into a design system for automatic circuit synthesis or for system simulation. Like Pascal, C and C++, VHDL includes features useful for structured design techniques, and offers a rich set of control and data representation features. Unlike these other programming languages, VHDL provides features allowing concurrent events to be described. This is important because the hardware described using VHDL is inherently concurrent in its operation.One of the most important applications of VHDL is to capture the performance specification for a circuit, in the form of what is monly referred to as a test bench. Test benches are VHDL descriptions of circuit stimuli and corresponding expected outputs that verify the behavior of a circuit over time. Test benches should be an integral part of any VHDL project and should be created in tandem with other descriptions of the circuit.A standard languageOne of the most pelling reasons for you to bee experienced with and knowledgeable in VHDL is its adoption as a standard in the electronic design munity. Using a standard language such as VHDL virtually guarantees that you will not have to throw away and recapture design concepts simply because the design entry method you have chosen is not supported in a newer generation of design tools. Using a standard language also means that you are more likely to be able to take advantage of the most uptodate design tools and that you will have access to a knowledge base of thousands of other engineers, many of whom are solving problems similar to your own.A brief history of VHDLVHDL, which stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language, was developed in the