【正文】 early 1980s as a spinoff of a highspeed integrated circuit research project funded by the . Department of Defense. During the VHSIC program, researchers were confronted with the daunting task of describing circuits of enormous scale (for their time) and of managing very large circuit design problems that involved multiple teams of engineers. With only gatelevel design tools available, it soon became clear that better, more structured design methods and tools would be needed.To meet this challenge, a team of engineers from three panies ?IBM, Texas Instruments and Intermetrics ?were contracted by the Department of Defense to plete the specification and implementation of a new, languagebased design description method. The first publicly available version of VHDL, version , was released in 1985. In 1986, the Institute of Electrical and Electronics Engineers, Inc. (IEEE) was presented with a proposal to standardize the language, which it did in 1987 after substantial enhancements and modifications were made by a team of mercial, government and academic representatives. The resulting standard, IEEE 10761987, is the basis for virtually every simulation and synthesi product sold today. An enhanced and updated version of the language, IEEE 10761993, was released in 1994, and VHDL tool vendors have been responding by adding these new language features to their products.Although IEEE Standard 1076 defines the plete VHDL language, there are aspects of the language that make it difficult to write pletely portable design descriptions (descriptions that can be simulated identically using different vendors?tools). The problem stems from the fact that VHDL supports many abstract data types, but it does not address the simple problem of characterizing different signal strengths or monly used simulation conditions such as unknowns and highimpedance. Soon after IEEE 10761987 was adopted, simulator panies began enhancing VHDL with new, nonstandard types to allow their customers to accurately simulate plex electronic circuits. This caused problems because design descriptions entered into one simulator were often inpatible with other simulation environments. VHDL was quickly being a nonstandard.To get around the problem of nonstandard data types, another standard was developed by an IEEE mittee. This standard, numbered 1164, defines a standard package (a VHDL feature that allows monly used declarations to be collected into an external library) containing definitions for a standard ninevalued data type. This standard data type is called std_logic, and the IEEE 1164 package is often referred to as the Standard Logic package. The IEEE 10761987 and IEEE 1164 standards together form the plete VHDL standard in widest use today. (IEEE 10761993 is slowly working its way into the VHDL mainstream, but it does not add significant new features for synthesis users.)Standard (often called the Numeric Standard or Synthesis Standard) defines standard packages and interpretations for VHDL data types as they relate to actual hardware. This standard, which was released at the end of 1995, is intended to replace the many custom (nonstandard) packages that vendors of synthesis tools have created and distributed with their products.IEEE Standard does for synthesis users what IEEE 1164 did for simulation users: increase the power of Standard 1076, while at the same time ensuring patibility between different vendors?tools. The standard includes, among other things:1) A documented hardware interpretation of values belonging to the bit and boolean types defined by IEEE Standard 1076, as well as interpretations of the std_ulogic type defined by IEEE Standard 1164.2) A function that provides donamp。care or wild card testing of values based on the std_ulogic type. This is of particular use for synthesis, since it is often helpful to express logic in terms of don抰 care values.3) Definitions for standard signed and unsigned arithmetic data types, along with arithmetic, shift, and type conversion operations for those types.The annotation of timing information to a simulation model is an important aspect of accurate digital simulation. The VHDL 1076 standard describes a variety of language features that can be used for timing annotation. However, it does not describe a standard method for expressing timing data outside of the timing model itself. The ability to separate the behavioral description of a simulation model from the timing specifications is important for many reasons. One of the major strengths of Verilog HDL (VHDL抯 closest rival) is the fact that Verilog HDL includes a feature specifically intended for timing annotation. This feature, the Standard Delay Format, or SDF, allows timing data to be expressed in a tabular form and included into the Verilog timing model at the time of simulation.The IEEE standard, published by the IEEE in late 1995, adds this capability to VHDL as a standard package. A primary impetus behind this standard effort (which was dubbed VITAL, for VHDL Initiative Toward ASIC Libraries) was to make it easier for ASIC vendors and others to generate timing models applicable to both VHDL and Verilog HDL. For this reason, the underlying data formats of IEEE and Verilog SDF are quite similar.When should you use VHDL?Why choose to use VHDL for your design efforts? There are many likely reasons. If you ask most VHDL tool vendors this question, the first answer you will get is, It will improve your productivity. But just what does this mean? Can you really expect to get your projects done faster using VHDL than by using your existing design methods?The answer is yes, but probably not the first time you use it, and only if you apply VHDL in a structured manner. VHDL (like a structured software design language) is most beneficial when you use a structured, topdown approach to design. Real increases in productivity will e later, when