【正文】 rrent (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.Port 3 also receives some control signals for Flash programming and programming verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcrontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.Pin Description (Continued)EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage (VPP) during Flash programming when 12volt programming is selected.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the onchip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) arethe Capture/Reload registers for Timer 2 in 16bit capture mode or 16bit autoreload mode.Special Function Registers (Continued)Interrupt Registers The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Data MemoryThe AT89C52 implements 256 bytes of onchip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.AT89C52主要性能參數：l 與MCS51產品指令和引腳完全兼容l 8K字節(jié)可重復檫寫FLASH閃速存儲器l 1000次檫寫周期l 全靜態(tài)操作：0HZ24HZl 三級加密程序存儲器l 256X8字節(jié)內容RAMl 32個可編程I/O口線l 3個16位定時/計數器l 8個中斷源l 可編程串行UART通道l 低功耗空閑和掉電模式功能特性概述：AT89C52提供以下標準功能：8K字節(jié)閃速存儲器，256字節(jié)內部RAM，32個I/O口線，3個16位定時/計數器，一個6向量兩極中斷結構，一個全雙工串行通信口，片內振蕩器及時鐘電路?？臻e方式停止CPU的工作，但允許RAM，定時/計數器，串行通信口及中斷系統(tǒng)繼續(xù)工作。引腳功能說明l VCC：電源電壓l GND：地l P0口：P0口是一組8位漏極開路雙向I/O口，也即地址/數據總線服用口。在訪問外部數據存儲器或 程序存儲器時，這組口線分時轉換地址和數據總線復用，在訪問激活內部上拉電阻。l P1口：是一個帶內部上拉電阻的8位雙響I/O口，P1輸出緩沖級可驅動4個TTL邏輯門電路。做輸入口。l P2口：是一個帶有內部上拉電阻的8位雙響I/O口，P2的輸出緩沖可驅動4個TTL邏輯門電路。在訪問外部程序存儲器或16位地址的外部數據存儲器時，P2口送出高8位地址數據。l P3口：P3口是一組帶有內部上拉電阻的8位雙響I/O口。對P3口寫入“1“時間，它們被內部上拉電阻拉高并可作為輸入斷口。P3口除了作為一般的I/O口線外，更重要的用途是它的第二功能。l RST：復位輸入。l ALE/PROG；當訪問外部程序存儲器或數據存儲器時ALE輸出脈沖用語鎖存地址的低8位字節(jié)。要注意的是：每當訪問外部數據存儲器時間、將跳過一個ALE脈沖。l PSEN：程序存儲允許輸出是外部程序存儲器的讀選通信號，當AT89C52由外部程序存儲器取指令時，每個機器周期量詞有效，即輸出兩個脈沖。l EA/VPP：外部訪問允許。需注意的是；如果加密LB1被編程，復位時內部會鎖存EA端狀態(tài)。FLASH存儲器編程時間，該引腳加上+12的變成允許電源，當然這必須是該器件是使用12編程電壓。對沒有定義的單元讀寫是無效的，讀出的數值將不確定，而寫入的數據也將丟失。l 中斷寄存器：AT89C52有6個中斷源，2個中斷優(yōu)先級，IE寄存器控制各中斷位，IP寄存器中6個中斷源的每一個可定為2個優(yōu)先級。當一條指令訪問7FH以上的內部地址單元時，指令中使用的尋址方式是不同的，也即尋址方式決定是訪問高128字節(jié)RAM還是訪問特殊寄存器。28