非同步電路設(shè)計(jì)-閱讀頁
2024-09-22 14:56本頁面
【正文】 l transition is enabled it must take place, . it must not be disabled by another signal transition. The STG specification of the circuit must guarantee persistency of internal signals (state variables) and output signals, whereas it is up to the environment to guaranteepersistency of the input signals. (6) Complete state coding (CSC): Two or more different markings of the STG must not have the same signal values (. correspond to the same state). If this is not the case, it is necessary to introduce extra state variables such that different markings correspond to different states. The synthesis tool Petrify will do this automatically. 18. (12%)In the timing diagram, a and b are inputs and c and d are outputs. According to the diagram, draw its STG and SG, and then design c and d.(623) (1) STG (2)SG a b c d abcdd+ a a+ b+ c c+ b b+ c+ d RR00 b+ 01R0 c+ 0F10 a+ b+ 1R00 110R c 00F0 b d+ 11R1 a F110 111F d c+ (3) The Karnaugh map of c (4) The Karnaugh map of d 00 01 00 01 11 10 cd\ab 0 R 0 0 x x R x x x 1 x F 1 1 x 11 10 00 01 11 10 cd\ab 00 01 0 0 R 0 x x 1 x x x F x 0 0 0 x 11 10 C c=d+a’ b+bc abcd or set(c)=d+a’b reset(c)=b’ Ccabd d=abc’ a b c d or set(d)=abc’ reset(d)=c a b c d 19. (3%)What is the static type checking in asynchronous circuit? (pp 118) 由於在不同 data validity的元件連結(jié)時(shí)，可能取擷取到 invalid 的 data 而發(fā)生錯(cuò)誤，所以在建構(gòu)完電路後必須檢查連接處的 data validity的正確性， data validity有其強(qiáng)弱性，強(qiáng)的可以包容弱的，但強(qiáng)的不可傳給弱的。
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