【正文】 the ADC to oversample channel 1 by 8x using sequencer 0. // Sequencer will be triggered by one of the generalpurpose timers. // ADCSequenceConfigure(ADC_BASE, 0, ADC_TRIGGER_TIMER, 0)。 ADCSoftwareOversampleStepConfigure(ADC_BASE, 0, 0, (ADC_CTL_CH1 \ | ADC_CTL_IE | ADC_CTL_END))。 TimerLoadSet(TIMER0_BASE, TIMER_A, SysCtlClockGet() / 100)。 The ADC configuration shown in Code Segment dictates that an interrupt occur when sampling pletes, meaning that an interrupt handler must be implemented (see Code Segment ). Since the Driver Library oversampling functions automatically average the sampled data, the interrupt handler function is relatively basic. Keep in mind that having the average calculated during each interrupt adds putational overhead to the interrupt handler. Code Segment . ADC Interrupt Handler void ADCIntHandler(void) { long lStatus。 // // Get averaged data from the ADC // lStatus = ADCSoftwareOversampleDataGet(ADC_BASE, 0, amp。 // // Placeholder for ADC processing code // } With the configuration steps and interrupt handler in place, the conversion process 6 is initiated. Before the timer is turned on (begins counting), the ADC sequencer and interrupt must be enabled (see Code Segment ). Code Segment . Enabling the ADC and Interrupts // // Enable ADC sequencer 0 and its interrupt (in both the ADC and NVIC) // ADCSequenceEnable(ADC_BASE, 0)。 IntEnable(INT_ADC0)。 Oversampling More Than 8 Times Using Multiple Sequencers or a Timer The Driver Library oversampling functions are limited to over sampling by 8 times (based on hardware limitations of the sample sequencers), meaning that applications requiring larger over sampling factors must use an alternative implementation. This section shows how to approach such a situation using two methods: multiple sample sequencers and a timer running at the oversampling frequency. Example 2. 16x Oversampling Using Multiple Sample Sequencers Figure 4. Oversampling by 16 7 Code Segment configures a 10ms periodic conversion using sequencers 02. A single timer trigger is used to initiate sampling on all 3 sequencers, eliminating the need for plex trigger configurations. To obtain the desired result, the sample sequencer priorities are configured such that sample sequencer 2 has the lowest priority (meaning it samples last), and the “ end of conversion” interrupt is configured to assert after the last step of sample sequence 2 (as shown in Figure 4). Code Segment . ADC Configuration – Multiple Sample Sequencers // // Initialize the ADC for 16x oversampling on channel 1 using sequencers // 02. The conversion is triggered by a GPTM. // ADCSequenceConfigure(ADC_BASE, 0, ADC_TRIGGER_TIMER, 0)。 ADCSequenceConfigure(ADC_BASE, 2, ADC_TRIGGER_TIMER, 2)。 ADCSequenceStepConfigure(ADC_BASE, 0, 1, ADC_CTL_CH1)。 ADCSequenceStepConfigure(ADC_BASE, 0, 3, ADC_CTL_CH1)。 ADCSequenceStepConfigure(ADC_BASE, 0, 5, ADC_CTL_CH1)。 ADCSequenceStepConfigure(ADC_BASE, 0, 7, (ADC_CTL_CH1 | ADC_CTL_END))。 ADCSequenceStepConfigure(ADC_BASE, 1, 1, ADC_CTL_CH1)。 ADCSequenceStepConfigure(ADC_BASE, 1, 3, (ADC_CTL_CH1 | ADC_CTL_END))。 ADCSequenceStepConfigure(ADC_BASE, 2, 1, ADC_CTL_CH1)。 ADCSequenceStepConfigure(ADC_BASE, 2, 3, (ADC_CTL_CH1 | ADC_CTL_IE \ | ADC_CTL_END))。 unsigned long ulSum = 0。 // // Get the data from sequencer 0 // for(ulIdx = 8。 ulIdx) 9 { ulSum += HWREG(ADC_BASE + ADC_O_SSFIFO0)。 ulIdx。 ulSum += HWREG(ADC_BASE + ADC_O_SSFIFO2)。 // // Placeholder for ADC processing code // } Before initiating the conversion process, the sample sequencers and interrupts are enabled (see Code Segment ). Code Segment . Enabling the ADC and Interrupts // // Enable the sequencers and interrupt // ADCSequenceEnable(ADC_BASE, 0)。 ADCSequenceEnable(ADC_BASE, 2)。 IntEnable(INT_ADC2)。 Example 3. 16x Oversampling Using a Timer Running at fOS Another way to over sample (without consuming a large portion of the ADC sequencer resources) is by using a periodic timer that runs at the over sampling frequency. For example, if a conversion must be returned to the main application every 10 ms and is to be over sampled by 16, a timer can be configured to take a single sample every 625 μs. Having the timer trigger a conversion at the over sampling frequency obviously generates additional ADC interrupt traffic, which must 10 be accounted for in the application. The code that configures the ADC and timer to operate like this is shown in Code Segment . Code Segment . ADC Configuration – Timer Running at fOS // // Initialize the ADC to take a single sample on channel 1, sequencer 3 // when a trigger is detected. // ADCSequenceConfigure(ADC_BASE, 3, ADC_TRIGGER_TIMER, 0)。 // // Initialize Timer 0 to trigger an ADC conversion once every 625 microseconds // TimerConfigure(TIMER0_BASE, TIMER_CFG_32_BIT_PER)。 TimerControlTrigger(TIMER0_BASE, TIMER_A, true)。 // // Add the new sample to the global sum // g_ulSum += HWREG(ADC_BASE + ADC_O_SSFIFO3)。 // // If 16 samples have accumulated, average them and reset globals // if(g_ucOversampleCnt == 16) { 11 g_ulAverage = g_ulSum 4。 g_ulSum = 0。 ADCIntEnable(ADC_BASE, 3)。 // // Zero the oversample counter and the sum // g_ucOversampleCnt = 0。 // // Enable the timer and start conversion process // TimerEnable(TIMER0_BASE, TIMER_A)。 ADCSequenceStepConfigure(ADC_BASE, 3, 0, (ADC_CTL_CH1 | ADC_CTL_IE \ | ADC_CTL_END))。 TimerLoadSet(TIMER0_BASE, TIMER_A, SysCtlClockGet() / 10000)。 Th