外文翻譯--三相電壓型pwm整流器建模和仿真研究-在線瀏覽
2024-10-02 17:13本頁面
【正文】 ith both coupling voltages ωLiq and ωLid, and main voltages ud and uq besides the influence of urd and and urq in the equations(1)and(2)can be regulated to ensure the correctness of equations(4)and(5). Putting equation (4)and(5)into equation(1)and(2)the nonlinear expression is such that the final relation between the controlled variables and the new inputs is linear and decoupled. Thus,the expected relations in the VSR are,We can see from equation that the two axis current are totally decoupled. urd’ and urq, are only related with id and iq simple proportionalintegral(PI)controllers are adopted in the current and voltage regulation. Design of outer voltage square loopEquation (3) describes the dynamics of vdc. Power balance equation can be used to derive an alternate equation for vdc dynamics. The active power absorbed from the ac source(Pac) and the active power delivered to the converter dcside (Pdc) are expressed by: The relationship between Pac and Pdc is: Pac=Pdc+Ploss (10) Where Ploss includes the power loss in the resistor R as well as the switching and conduction losses in the VSR. The resistance R is always very small and thus it is practically reasonable to neglect its power loss. The rectifier losses are larger than the power loss in R but still they count for a small portion of the total power. Therefore,the rectifier losses can also be neglected without noticeable loss of accuracy. If better accuracy is desired the rectifier losses can be represented by a small resistor in series with RL. The total equivalent dcside resistance is still represented by RL. From Pac=Pdc,the following dynamic results: Which can be rearranged in following form: Due to unidirectional nature of vdc ,Taking vdo2 as the variable,(12) will bee linear.Putting equation (8) into equation(12),This is a firstorder dynamic equation with vdc2 as the state variable as well as the output,and Pac as the input. A simple PI controller can be designed to regulate the DC voltage with no steady state error. Since ud is measurable,the actual input variable id can be derived from Pac. The result is actually the reference value of id for the current inner control loop. displays inner current loop with state feedback decoupling and outer voltage square loop control system for VSR. Block diagram of double closeloop control for threephase VSR2 Voltage Spacevector SynthesizationWhen the urd and urq acquired the SVPWM method is realized through dq to αβtransformation to trace the AC current mand exactly and regulate the DC bus voltage. Depending on the switching state on the circuit the bridge rectifier leg voltages can assume 8 possible distinct states represented as voltage vectors (V0 to V7). V1 to V6 are six fixed nonzero vectorsV0 and V7 are two zero vectors as shown in the input three phase voltage are divided into six 60176。 intervals it satisfies that the signs of the amp
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