【正文】 附錄 A：中文譯文低壓CMOS帶隙基準(zhǔn)電壓源設(shè)計(jì)摘要：基準(zhǔn)源是模擬集成電路中的基本單元之一, 它在高精度 ADC, DAC, SoC 等電路中起著重要作用, 基準(zhǔn)源的精度直接控制著這些電路的精度。并基于CSMC m Double Poly M ix Process 對(duì)電路進(jìn)行了仿真, 得到理想的設(shè)計(jì)結(jié)果。 低功耗。 高電源抑制比0 引言基準(zhǔn)電壓源廣泛應(yīng)用于電源調(diào)節(jié)器、 D 和 D/ A 、A/D轉(zhuǎn)換器、數(shù)據(jù)采集系統(tǒng), 以及各種測(cè)量設(shè)備中。比如, 在一些使用電池的系統(tǒng)中, 要求電源 電壓在 3 V 以下。在傳統(tǒng)的 帶隙基 準(zhǔn)源 設(shè)計(jì)中, V 左右, 這就限制了最小電源電壓。近年來(lái), 一些文獻(xiàn)力圖解決這方面的問題。 第二個(gè)問題可以通過(guò) BiCMOS 工藝來(lái)實(shí)現(xiàn) , 或通過(guò)低閾值電壓的 MOS 器件來(lái)實(shí)現(xiàn)但工藝上的難度以及設(shè)計(jì)成本將上升。本文介紹這種帶隙電壓基準(zhǔn)源的設(shè)計(jì)原理給出了電路的仿真結(jié)果, 并對(duì)結(jié)果進(jìn)行了分析。1 低壓COMS基準(zhǔn)電壓源設(shè)計(jì)圖1為帶隙基準(zhǔn)電壓源的原理示意圖。而熱電壓Vt具有正的溫度系數(shù), 其溫度系數(shù)在室溫下為+。Vbe受電源電壓變化的影響很小，因而帶隙基準(zhǔn)電壓的輸出電壓受電源的影響也很小。兩個(gè)PNP管Q1,Q2的基極發(fā)射極電壓差： （2）式中：j1和j2是流過(guò)Q1和Q2的電流密度。即： （3） （4）圖1 帶隙基準(zhǔn)源原理示意圖圖2 典型的CMOS帶隙電壓基準(zhǔn)源由圖2可得： (5)通過(guò)M1和M2的鏡像作用，使得I1和I2相等，結(jié)合式（4）和式（5）可得： (6)式中：A1和A2是Q1和Q2的發(fā)射極面積。傳統(tǒng)帶隙基準(zhǔn)源結(jié)構(gòu)能輸出比較精確的電壓，但其電源電壓較高（大于3V），且基準(zhǔn)輸出范圍有限（）以下的精確基準(zhǔn)電壓，就必須對(duì)基準(zhǔn)源結(jié)構(gòu)上進(jìn)行改進(jìn)和提高。低壓帶隙基準(zhǔn)源的電流不僅用于提供基準(zhǔn)輸出所需的電流，也用于產(chǎn)生差分放大器所需的電流源偏置電壓，簡(jiǎn)化了電路和版圖設(shè)計(jì)。Q2和Q1的發(fā)射極面積比為8：1，流過(guò)Q1和Q2的電流相等，這樣等于Vtln8。三路鏡像電流源使得流過(guò)P2，P3，P4的電流相等（I1=I2=I3）。在電源電壓變化時(shí), P2 , P3 , P4 的漏源電壓值保持不變, 與電源電壓無(wú)關(guān), 其柵極電壓由運(yùn)放調(diào)節(jié)。因?yàn)檎麄€(gè)電路在低壓下工作, 故整個(gè)電路設(shè)計(jì)的重點(diǎn)是要保證低壓下運(yùn)放的正常工作。當(dāng)基準(zhǔn)源工作在零點(diǎn)時(shí), 節(jié)點(diǎn)2 的電壓等于零, 基準(zhǔn)源沒有電流產(chǎn)生。本設(shè)計(jì)的啟動(dòng)電路由NN6 和P7 構(gòu)成。電路的器件參數(shù)如表 1 所示, P2 , P3 , P4 管的尺寸較大, 是為了降低電路中的1/ f 噪聲。由于電路中的電阻值較大, 故在工藝中用阱電阻實(shí)現(xiàn)。2 仿真與結(jié)果分析在Cadence 設(shè)計(jì)平臺(tái)下的Spectre 仿真器中基于CSMC 。各項(xiàng)仿真結(jié)果參數(shù)如表2所示。~4V, 工作溫度為 10~ + 130 ℃ , 基準(zhǔn)輸出電壓Vref為,℃，電源抑制比為70dB。附錄 B： 外文譯文Low voltage CMOS bandgap reference voltage sourceAbstractReference is a simulation of one of the basic unit in integrated circuits. It is in high accuracy of ADC, DAC, SoC plays an important role in circuit. Reference source accuracy directly control the circuit accuracy, Paper based on a bandgap reference structure Sub 1 V, low power consumption, CMOS reference voltage source than the temperature coefficient, low and high power supply rejection. And based on the CSMC m Double Poly M ix Process .The simulation of the circuit design, obtained ideal results.Keywords: CMOS reference voltage source。 Sub 1 V。s circuit design. For example, in some use the battery, required power supply voltage below 3 V. Therefore, A/D as a regulator, D and D/ A converter circuit core function module of the reference source, pressure, inevitable requirement of working under low voltage supply. In the traditional bandgap reference source in the design, the output voltage constant at about V, which limits the minimum supply voltage. On the other hand, the monmode input voltage range mon collector parasitic BJT and operational amplifier, also limits the design pressure PTAT current loop. In recent years, some of the literature to solve this problem. To sum up, before the problem can be solved by an appropriate resistive divider to achieve。s baseemitter voltage difference: (2)Type: J1 and J2 is the current density flowing in Q1 and Q2. Operational amplifier circuit in the depth of the negative feedback mode, the node 1 and node voltage is equal to 2. That is: (3) (4)Fig. 1 Schematic diagram of bandgap reference source principle typical CMOS bandgap voltage referenceFig. 2 available: (5)Through the mirror effect of M1 and M2, which makes the I1 and I2 are equal, bined (4) and (5) available: (6)Type: A1 and A2 are Q1 and Q2 emitter area. Comparing (5) and (1), available for constant K: (7)In practical design, the K value is the type (7) said.Output voltage can accurate bandgap reference structure of traditional band, but the power supply voltage is higher (more than 3V), and the reference output range is limited () precision reference voltage below, we must improve the reference structure. Circuit design of low voltage CMOS bandgap voltage sourceThe design is based on Technology (NMOS threshold voltage is , the threshold voltage of PMOS to ), using a temperature pensation, current feedback voltage technology design of the bandgap reference circuit as shown in figure 3. Low voltage bandgap reference not only for the current reference output required, is also used to produce differential current source bias voltage required by the differential amplifier, simplifies the circuit and layout design.In order to be patible with standard CMOS technology, circuit of the PNP e, B, C respectively by P+, Nwell, Psub grounded collector. The emitter area of Q2 and Q1 ratio is 8:1, current flowing through the Q1 and Q2 are equal, this is equal to Vtln8. Current through resistor R1 and proportional to the thermodynamic temperature. Three way mirror current source that flows through P2, P3, current equal to P4 (I1=I2=I3).Fig. 3 the whole circuit diagramOutput voltage Vref:K circuit for temperature pensation coefficient:By adjusting the R4 value, can adjust the output voltage of Vref size. Variations in supply voltage, P2, P3, drain source voltage P4 values remained unchanged, regardless of the supply voltage, the gate voltage regulation by operational amplifier. In order to reduce the plexity of the application circuit, current feedback operational amplifier by using the firstorder operational principle, simple, due to changes in Vdd changes more than GND, so the operational amplifier input using NMOS differential pair structure. Because the entire circuit in lowPress work, focusing on the whole circuit design is to ensure the normal work under low voltage operational amplifier.The bandgap reference circuit has two equilibrium points, namely the zeros and the normal operating point. When the reference work in zero, voltage node 1, 2 is equal to zero, no current reference source. Solid need to design a starting circuit.Road, avoid reference work in balance zero. The startup circuit designed by N5, N6 and P7. When the circuit is working at zero, the N6 pass, rapidly improve the voltage node 1, 2, generating a reference current, the inverter voltage node 1 by P7 and N5, the N6 tube pletely cuto