【正文】 2/8/17 7 HW Schemes: Instruction Parallelism ? Will distinguish when an instruction begins execution and when it pletes execution。 between 2 times, the instruction is in execution ? When and Where in a pipeline? ? Note: Dynamic execution creates WAR and WAW hazards and makes exceptions harder ? Why it can create WAR and WAW? 2022/8/17 8 Dynamic Scheduling Step 1 ? Simple pipeline had 1 stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue ? Split the ID pipe stage of simple 5stage pipeline into 2 stages: ? Issue— Decode instructions, check for structural hazards ? Read operands— Wait until no data hazards, then read operands ? Understand? Ex IS Ex Wb 2022/8/17 9 A Dynamic Algorithm: Tomasulo’s ? For IBM 360/91 (before caches!) –? Long memory latency ? Goal: High Performance without special pilers ? Small number of floating point registers (4 in 360) prevented interesting piler scheduling of operations –This led Tomasulo to try to figure out how to get more effective registers — renaming in hardware! ? Why Study 1966 Computer? ? The descendants of this have flourished! –Alpha 21264, Pentium 4, AMD Opteron, Power 5, … 2022/8/17 10 Tomasulo Algorithm ? Control amp。 have pending operands ? Registers in instructions replaced by values or pointers to reservation stations(RS)。 –Renaming avoids WAR, WAW hazards –More reservation stations than registers, so can do optimizations pilers can’t 2022/8/17 11 Tomasulo Algorithm ? Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs –Avoids RAW hazards by executing an instruction only when its operands are available ? Load and Stores treated as FUs with RSs as well ? Integer instructions can go past branches (predict taken), allowing FP ops beyond basic block in FP queue 2022/8/17 12 Tomasulo Organization FP adders Add1 Add2 Add3 FP multipliers Mult1 Mult2 From Mem FP Registers Reservation Stations Common Data Bus (CDB) To Mem FP Op Queue Load Buffers Store Buffers Load1 Load2 Load3 Load4 Load5 Load6 2022/8/17 13 Reservation Station Components Op: Operation to perform in the unit (., + or –) Vj, Vk: Value of Source operands –Store buffers has V field, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) –Note: Qj,Qk=0 = ready –Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. 2022/8/17 14 Three Stages of Tomasulo Algorithm 1. Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr amp。 if not ready, watch Common Data Bus for result 3. Write result—finish execution (WB) Write on Common Data Bus to all awaiting units。 –10 clocks for Flopt. * 。 MULT issued ? Load1 pleting。 what is waiting for Load2? 2022/8/17 21 Tomasulo Example Cycle 5 I ns tr uc ti on s tat us : E xec W r i t eIns t ruc t i on j k Is s u e Co m p R es u l t Bu s y A d d res sLD F6 34+ R2 1 3 4 L oa d1 NoLD F2 45+ R3 2 4 5 L oa d2 NoM U L T D F0 F2 F4 3 L oa d3 NoS U BD F8 F6 F2 4D IV D F 10 F0 F6 5ADDD F6 F8 F2R e s e r v ati on Stat ions : S1 S2 RS RST i m e Nam e Busy Op Vj Vk Qj Qk2 A dd1 Y e s S U BD M (A 1) M (A 2)A dd2 NoA dd3 No10 M ul t 1 Y e s M U L T D M (A 2) R(F 4)M ul t 2 Y e s D IV D M (A 1) M ul t 1R e gis te r r e s ult s tat us :C loc k F0 F2 F4 F6 F8 F 10 F 12 ... F 305 FU M ul t 1 M (A 2) M (A 1) A dd1 M ul t 2? Timer starts down for Add1, Mult1 2022/8/17 22 Tomasulo Example Cycle 6 I ns tr uc ti on s tat us : E xec W r i t eIns t ruc t i on j k Is s u e Co m p R es u l t Bu s y A d d res sLD F6 34+ R2 1 3 4 L oa d1 NoLD F2 45+ R3 2 4 5 L oa d2 NoM U L T D F0 F2 F4 3 L oa d3 NoS U BD F8 F6 F2 4D IV D F 10 F0 F6 5ADDD F6 F8 F2 6R e s e r v ati on Stat ions : S1 S2 RS RST i m e Nam e Busy Op Vj Vk Qj Qk1 A dd1 Y e s S U BD M (A 1) M (A 2)A dd2 Y e s ADDD M (A 2) A dd1A dd3 No9 M ul t 1 Y e s M U L T D M (A 2) R(F 4)M ul t 2 Y e s D IV D M (A 1) M ul t 1R e gis te r r e s ult s tat us :C loc k F0 F2 F4 F6 F8 F 10 F 12 ... F 306 FU M ul t 1 M (A 2) A dd2 A dd1 M ul t 2? Issue ADDD here despite name dependency on F6? 2022/8/17 23 Tomasulo Example Cycle 7 I ns tr uc ti on s tat us : E xec W r i t eIns t ruc t i on j k Is s u e Co m p R es u l t Bu s y A d d res sLD F6 34+ R2 1 3 4 L oa d1 NoLD F2 45+ R3 2 4 5 L oa d2 NoM U L T D F0 F2 F4 3 L oa d3 NoS U BD F8 F6 F2 4 7D IV D F 10 F0 F6 5ADDD F6 F8 F2 6R e s e r v ati on Stat ions : S1 S2 RS RST i m e Nam e Busy Op Vj Vk Qj Qk0 A dd1 Y