現(xiàn)代計(jì)算機(jī)體系結(jié)構(gòu)-wenkub.com
2025-07-17 03:08 本頁面
【正文】 what is waiting for it? 2022/8/17 36 Tomasulo Example Cycle 57 I ns tr uc ti on s tat us : E xec W r i t eIns t ruc t i on j k Is s u e Co m p R es u l t Bu s y A d d res sLD F6 34+ R2 1 3 4 L oa d1 NoLD F2 45+ R3 2 4 5 L oa d2 NoM U L T D F0 F2 F4 3 15 16 L oa d3 NoS U BD F8 F6 F2 4 7 8D IV D F 10 F0 F6 5 56 57ADDD F6 F8 F2 6 10 11R e s e r v ati on Stat ions : S1 S2 RS RST i m e Nam e Busy Op Vj Vk Qj QkA dd1 NoA dd2 NoA dd3 NoM ul t 1 NoM ul t 2 Y e s D IV D M *F 4 M (A 1)R e gis te r r e s ult s tat us :C loc k F0 F2 F4 F6 F8 F 10 F 12 ... F 3056 FU M *F 4 M (A 2) (M M + M )(M M ) Re s ul t? Once again: Inorder issue, outoforder execution and outoforder pletion. 2022/8/17 37 Why can Tomasulo overlap iterations of loops? ? Register renaming –Multiple iterations use different physical destinations for registers (dynamic loop unrolling). ? Reservation stations –Permit instruction issue to advance past integer control flow operations –Also buffer old values of registers totally avoiding the WAR stall ? Other perspective: Tomasulo building data flow dependency graph on the fly 2022/8/17 38 Tomasulo’s scheme offers 2 major advantages 1. Distribution of the hazard detection logic – distributed reservation stations and the CDB – If multiple instructions waiting on single result, amp。 what is waiting for Load2? 2022/8/17 21 Tomasulo Example Cycle 5 I ns tr uc ti on s tat us : E xec W r i t eIns t ruc t i on j k Is s u e Co m p R es u l t Bu s y A d d res sLD F6 34+ R2 1 3 4 L oa d1 NoLD F2 45+ R3 2 4 5 L oa d2 NoM U L T D F0 F2 F4 3 L oa d3 NoS U BD F8 F6 F2 4D IV D F 10 F0 F6 5ADDD F6 F8 F2R e s e r v ati on Stat ions : S1 S2 RS RST i m e Nam e Busy Op Vj Vk Qj Qk2 A dd1 Y e s S U BD M (A 1) M (A 2)A dd2 NoA dd3 No10 M ul t 1 Y e s M U L T D M (A 2) R(F 4)M ul t 2 Y e s D IV D M (A 1) M ul t 1R e gis te r r e s ult s tat us :C loc k F0 F2 F4 F6 F8 F 10 F 12 ... F 305 FU M ul t 1 M (A 2) M (A 1) A dd1 M ul t 2? Timer starts down for Add1, Mult1 2022/8/17 22 Tomasulo Example Cycle 6 I ns tr uc ti on s tat us : E xec W r i t eIns t ruc t i on j k Is s u e Co m p R es u l t Bu s y A d d res sLD F6 34+ R2 1 3 4 L oa d1 NoLD F2 45+ R3 2 4 5 L oa d2 NoM U L T D F0 F2 F4 3 L oa d3 NoS U BD F8 F6 F2 4D IV D F 10 F0 F6 5ADDD F6 F8 F2 6R e s e r v ati on Stat ions : S1 S2 RS RST i m e Nam e Busy Op Vj Vk Qj Qk1 A dd1 Y e s S U BD M (A 1) M (A 2)A dd2 Y e s ADDD M (A 2) A dd1A dd3 No9 M ul t 1 Y e s M U L T D M (A 2) R(F 4)M ul t 2 Y e s D IV D M (A 1) M ul t 1R e gis te r r e s ult s tat us :C loc k F0 F2 F4 F6 F8 F 10 F 12 ... F 306 FU M ul t 1 M (A 2) A dd2 A dd1 M ul t 2? Issue ADDD here despite name dependency on F6? 2022/8/17 23 Tomasulo Example Cycle 7 I ns tr uc ti on s tat us : E xec W r i t eIns t ruc t i on j k Is s u e Co m p R es u l t Bu s y A d d res sLD F6 34+ R2 1 3 4 L oa d1 NoLD F2 45+ R3 2 4 5 L oa d2 NoM U L T D F0 F2 F4 3 L oa d3 NoS U BD F8 F6 F2 4 7D IV D F 10 F0 F6 5ADDD F6 F8 F2 6R e s e r v ati on Stat ions : S1 S2 RS RST i m e Nam e Busy Op Vj Vk Qj Qk0 A dd1 Y e s S U BD M (A 1) M (A 2)A dd2 Y e s ADDD M (A 2) A dd1A dd3 No8 M ul t 1 Y e s M U L T D M (A 2) R(F 4)M ul t 2 Y e s D IV D M (A 1) M ul t 1R e gis te r r e s ult s tat us :C loc k F0 F2 F4 F6 F8 F 10 F 12 ... F 307 FU M ul t 1 M (A 2) A dd2 A dd1 M ul t 2? Add1 (SUBD) pleting。 –10 clocks for Flopt. * 。 –Renaming avoids WAR, WAW hazards –More reservation stations than registers, so can do optimizations pilers can’t 2022/8/17 11 Tomasulo Algorithm ? Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs –Avoids RAW hazards by executing an instruction only when its operands are available ? Load and Stores treated as FUs with RSs as well ? Integer instructions can go past branches (predict taken), allowing FP ops beyond basic block in FP queue 2022/8/17 12 Tomasulo Organization FP adders Add1 Add2 Add3 FP multipliers Mult1 Mult2 From Mem FP Registers Reservation Stations Common Data Bus (CDB) To Mem FP Op Queue Load Buffers Store Buffers Load1 Load2 Load3 Load4 Load5 Load6 2022/8/17 13 Reservation Station Components Op: Operation to perform in the unit (., + or –) Vj, Vk: Value of Source operands –Store buffers has V field, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) –Note: Qj,Qk=0 = ready –Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. 2022/8/17 14 Three Stages of Tomasulo Algorithm 1. Issue—get instruction from FP
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