【正文】 tion and delay based on the quantitative methods in a short period of time interval measurement, achieved within the scope of broadband, such as highresolution measurement accuracy. Quantified by measuring short time intervals Delay 、 6 Photoelectric signal can be in a certain stability in the medium of rapid spread, and in different media have different delay. By signals generated by the delay to quantify, and gave a short period of time interval measurement. The basic principle is that delay serial, parallel count, and different from the traditional counter serial number, that is, to signal through a series of delay unit, the delay unit on the delay stability, under the control of the puter Delay on the state of highspeed acquisition and data processing, for a short period of time to achieve accurate measurement interval. Delay quantitative thinking depend on the realization of the delay stability delay unit, the unit depends on the resolution of the delay time delay element. Delay device as a unit can be passive conduit, or other active devices gate circuit. Among them, Traverse shorter delay time (nearly the speed of light transmission delay), the gate delay time longer. Taking into account delays can be predictive ability final choice of the CPLD devices, the realization of the short time interval measurement. Will be the beginning of a short time interval signal sent delay in the transmission chain, when the advent of the end of signal, this signal delay in the delay in the chain latch state, read through the CPU, the judge signal a delay unit on the few shortterm time interval can be the size of the unit decided to delay resolution of the unit delay time. Generally speaking, in order to measure both short interval, the use of two modules delay and latches, but in reality, given the time software gate large enough to allow pletion from the number of CPU operation, which can be measured in the time interval taken before the end of a short period of time at Δ t1 corresponding delay the number of units through the control signals must be used only a delay and latches units, it saves CPLD internal resources. Synchronization and multicycle latency to quantify the method of bining The formula is: T=n0t0+n1t1n2t1 On, n0 for the filling pulse of value。 n1 for a short period of time at Δ t1 corresponding delay the number of modules。 t1 quantify delay devices for the 、 7 delay delay unit volume ( ns). In this way, using multicycle synchronization and realized the gate and measured signal synchronization。1107/s. When the measurement and quantification of delay circuit with short intervals bined, the uncertainty of measurement can be derived from the following. In the use of cycle synchronization, multianalyte Tx for the cycle value of T0 time base for the introduction of the cycle. Tx= NT0+△ t1△ t2 Delay circuit and quantitative bined: Tx= NT0+(N1N2)td177。2td From the details of the measuring accuracy of this method depends on the td, and its direct impact on the stability and size of the uncertainty of measurement. Therefore, the application of methods, counters can be achieved within the entire frequency range, such as the accuracy of measurement, and measurement accuracy is significantly improved, measuring improvement in resolution to ns, and the eli mination of the word 177。s useful to understand the overall VHDL design environment belbre jumping inlo the language itself. Thew aw several steps in a VHDL based design process, often called the deign flow. These steps are applicable to any HDL based design process and are outlined in Figure 1. 、 9 frontend steps (painful,but no unmon) (very painful!) backend steps Steps in a VHDL or other HDLbased design flow The socalled flont end begins with figuring out the basic approach and building blocks at the blockdiagram level. Large logic design, like software programs, are usually hierarchical, and VHDL gives you a good famework for defining modules and their interfaces and filling in the details later. The next step is the actual writing of VHDL code for modules, their interfaces, and their internal details. Since VHDL is a textbased language, in principle you can use any text editor for this part of the job. However, most design environments include a specialized VHDL text editor that makes the job a little easier。ve written some code, you will want to pile it, of course. A VHDL piler analyzes your code for syntax errors and also checks it for patibility with other modules on which it relies. It also creates the inlternal information that is needed for a simulator to process your design later. As in other programming endeavors, you probably shouldn39。s logical operation independent of timing considerations。s operation including estimated sequential devices like flipflops are met. It is customary to perform thorough functional verification before starting the backend steps. However, our ability to do timing verification at this stage is often limited, since timing may be heavily dependent on the results of synthesis and fitting .We may do preliminary timing verification to gain some fort with the overall design approach, but detailed timing verification must wait until the end.. After verification, we are ready to move into the backend stage The nature of and tools for this stage vary somewhat, depending on the target technology for the design, but there are three basic steps. The first is synthesis, converting the VHDL description into a set of primitive