【正文】 form and Cadence, ExemplarLogic, MentorGraphics, Synopsys and Synplicity EDA vendors and other development tools are patible. LogicLock improve the software module design features, added FastFit piler options, and promote the work editing performance, and improved debugging capabilities. MAX7000/MAX3000 devices and other items to support the product. 3. Development of language VHDL VHDL (Very High Speed Integrated Circuit Hardware Description Language) is a very high speed integrated circuit hardware description language, it can describe the function of the hardware circuitry, signal connectivity and the time between languages. It can be more effective than the circuit diagram to express the characteristics of the hardware circuit. Using the VHDL language, you can proceed to the general requirements of the system, since the detailed content will be designed to e down to earth, and finally to plete the overall design of the system hardware. IEEE VHDL language has been the industry standard as a design to facilitate reuse and sharing the results. At present, it can not be applied analog circuit design, but has been put into research. VHDL program structure, including: entity (Entity), structure (Architecture), configure (Configuration), Package Collection (Package) and the Library (Library). Among them, the entity is the basic unit of a VHDL program, by entity and the structure of two parts: the physical design system that is used to describe the external interface signal。s database. VHDL, the main features are: ① powerful, high flexibility: VHDL language is a powerful language structure, clear and concise code can be used to design plex control logic. VHDL language also supports hierarchical design, support design databases and build reusable ponents. Currently, VHDL language has bee a design, simulation, synthesis of standard hardware description language. ② Device independence: VHDL language allows designers to generate a design do not need to first select a specific device. For the same design description, you can use a variety of different device structures to achieve its function. So the design description stage, able to focus on design ideas. When the design, simulation, after the adoption of a specific device specified integrated, adapter can be. ③ Portability: VHDL language is a standard language, so the use of VHDL design can be carried out by different EDA tool support. Transplanted from one to another simulation tools simulation tools, synthesis tools from a port to another integrated tool, from a working platform into another working platform. EDA tools used in a technical skills, in other tools can also be used. ④ topdown design methods: the traditional design approach is bottomup design or flat design. Bottomup design methodology is to start the bottom of the module design, the gradual formation of the functional modules of plex circuits. Advantage of this design is obvious because it is a hierarchical circuit design, the general circuit submodule are in accordance with the structure or function of division, so the circuit level clear, clear structure, easy people to develop, while the design archive file is easy, easy munication. Bottomup design is also very obvious shortings, the overall design concept is often not leaving because the cost of months of lowlevel design in vain. Flat design is a module containing only the circuit, the circuit design is straightforward and, with no division structure and function, it is not hierarchical circuit design. Advantages of small circuit design can save time and effort, but with the increasing plexity of the circuit, this design highlights the shortings of the abnormal changes. Topdown design approach is to design toplevel circuit description (top model), and then the toplevel simulation using EDA software, if the toplevel design of the simulation results meet the requirements, you can continue to lower the toplevel module by the division level and simulation, design of such a level will eventually plete the entire circuit. Topdown design method pared with the first two are obvious advantages. ⑤ rich data types: as a hardware description language VHDL data types are very rich language, in addition to VHDL language itself dozens of predefined data types, in the VHDL language programming also can be userdefined data types. Std_logic data types in particular the use of VHDL language can make the most realistic plex signals in analog circuits. ⑥ modeling convenience: the VHDL language can be integrated in the statement