【正文】 初始相位值 (K2)，可以 調(diào)節(jié)兩路相同頻率正弦信號(hào)之間的相位差 ，從而產(chǎn)生數(shù)字式的頻率、相位和幅值可調(diào)的精密正弦波信號(hào)，最后通過(guò) MAX+PLUSII演示仿真結(jié)果?；?DDS 的精密正弦信號(hào)發(fā)生器的設(shè) 計(jì) I 基于 DDS 的精密正弦信號(hào)發(fā)生器的設(shè)計(jì) 摘 要 本設(shè)計(jì)采用了直接數(shù)字頻率合成（ DDS）技術(shù)來(lái)實(shí)現(xiàn)。側(cè)重?cái)⑹隽擞?FPGA 來(lái)完成直接數(shù)字頻率合成器 (DDS)的設(shè)計(jì)， DDS 由相位累加器和正弦 ROM 查找表兩個(gè)功能塊組成，其中 ROM 查找表由兆功能模塊 LPM_ROM 來(lái)實(shí)現(xiàn)。 與傳統(tǒng)的頻率合成方法相比， DDS 合成信號(hào)具有 頻率切換時(shí)間短、頻率分辨率高、相位變化連續(xù)等諸多優(yōu)點(diǎn)。 關(guān)鍵字 單片機(jī) DDS FPGA 正弦信號(hào)發(fā)生器 基于 DDS 的精密正弦信號(hào)發(fā)生器的設(shè) 計(jì) II DDSBASED PRECISION SINUSOIDAL SIGNAL GENERATOR ABSTRACT This design uses a direct digital frequency synthesis (DDS) technologies. Described with emphasis on FPGA to plete the direct digital synthesizer (DDS) design, DDS ROM from the phase accumulator and sine lookup table posed of two functional blocks, including ROM lookup table by the function module LPM_ROM trillion to implement. The accumulator by setting different initial (K1) and the initial phase value (K2), the same frequency can be adjusted two phase difference between the sinusoidal signal, resulting in digital, frequency, phase and amplitude adjustable precision sine wave signal, the final presentation by MAX + plus II simulation results. And pared to the traditional method of frequency synthesis, DDS synthesized signal with frequency switching time is short, high frequency resolution, phase change continuously, and many other advantages. Flexible control using microcontroller and FPGA device performance, highly integrated bination of design can overe the deficiencies of traditional DDS to design and develop excellent performance DDS system. KEY WORDS single chip puter DDS FPGA Sinusoidal signal generator 基于 DDS 的精密正弦信號(hào)發(fā)生器的設(shè) 計(jì) 目 錄 摘 要 ........................................................................................................................... I ABSTRACT ...................................................................................................................... II 1 緒論 ............................................................................................................................ 1 課題背景 .................................................................................................................. 1 研究此課題的目的和意義 .......................................................................................... 1 本文 主要研究的工作和目標(biāo) ...................................................................................... 2 2 設(shè)計(jì)方案的概述及論證 ................................................................................................ 4 系統(tǒng)的性能要求 ........................................................................................................ 4 方案論證與比較 ........................................................................................................ 4 方案確定 .................................................................................................................. 5 3 FPGA部分設(shè)計(jì) ........................................................................................................... 6 FPGA的簡(jiǎn)介 ............................................................................................................ 6 FPGA芯片的選擇 ..................................................................................................... 7 DDS原理及相關(guān)介紹 ................................................................................................ 9 各模塊發(fā)生原理 .......................................................................................................10 正弦波發(fā)生模塊原理 .............................................................................................10 AM 硬件實(shí)現(xiàn)原理 ................................................................................................. 11 FM 調(diào)制原理 ......................................................................................................... 11 ASK 調(diào) 制原理 .......................................................................................................12 FSK調(diào)制原理 .......................................................................................................12 正弦波發(fā)生模塊的實(shí)現(xiàn) ............................................................................................12 FPGA設(shè)計(jì) DDS 電路的具體實(shí)現(xiàn) .............................................................................14 相位累加器部分 ....................................................................................................14 相位 /幅度轉(zhuǎn)換電路 ................................................................................................14 波形表生成 ...........................................................................................................15 .........................................................................................................16 系統(tǒng)組成框圖 ..........................................................................................................16 D/A轉(zhuǎn)換電路 ..........................................................................................................16 DAC0832芯片簡(jiǎn)介 ...............................................................................................16 濾波電路 .................................................................................................................19 數(shù)碼管顯示電路 .......................................................................................................20 鍵盤(pán)接口電路 ..........................................................................................................20 5 系統(tǒng)的計(jì)算與仿真 ......................................................................................................22 MAX+plusⅡ軟件介紹 ............................................................................................22 基于 DDS 的精密正弦信號(hào)發(fā)生器的設(shè) 計(jì) 系統(tǒng)頻率、相位和幅度的 計(jì)算 ..................................................................................23 系統(tǒng)仿真 ..........................................................................