【正文】 2C)CANRIOC /* TX I/O control */define((REGS32U)0x00602A)CANTIOC /* Overwrite protection control */define ((REGS32U)0x006028)CANOPC /* Mailbox interrupt level */define ((REGS32U)0x006026)CANMIL /* Mailbox interrupt mask */define ((REGS32U)0x006024)CANMIM /* Global interrupt flag 1 */define ((REGS32U)0x006022)CANGIF1 /* Global interrupt mask */define ((REGS32U)0x006020)CANGIM /* Global interrupt flag 0 */define ((REGS32U)0x00601E)CANGIF0 /* Receive error counter */define ((REGS32U)0x00601C)CANREC /* Transmit error counter */define ((REGS32U)0x00601A)CANTEC /* Error and status */define ((REGS32U)0x006018)CANES /* Bittiming configuration */define ((REGS32U)0x006016)CANBTC /* Master control */define ((REGS32U)0x006014)CANMC /* Global acceptance mask */define((REGS32U)0x006012)CANGAM /* Remote frame pending */define ((REGS32U)0x006010)CANRFP /* Receive message lost */define ((REGS32U)0x00600E)CANRML /* Receive message pending */define((REGS32U)0x00600C)CANRMP /* Abort acknowledge */define ((REGS32U)0x00600A)CANAA /* Transmission acknowledge */define ((REGS32U)0x006008)CANTA /* Transmit request reset */define ((REGS32U)0x006006)CANTRR /* Transmit request set */define ((REGS32U)0x006004)CANTRS /* Mailbox direction */define ((REGS32U)0x006002)CANMD /* Mailbox enable */define ((REGS32U)0x006000)CANME/* CAN模塊控制寄存器 */define /* PIE, INT12 Group Flag Register *//**//*定義CAN模塊寄存器*//**/ ((REGS16U)0x000CF9)PIEIFR12 /* PIE, INT12 Group Enable Register */define((REGS16U)0x000CF8)PIEIER12 /* PIE, INT11 Group Flag Register */define ((REGS16U)0x000CF7)PIEIFR11 /* PIE, INT11 Group Enable Register */define((REGS16U)0x000CF6)PIEIER11 /* PIE, INT10 Group Flag Register */define ((REGS16U)0x000CF5)PIEIFR10 /* PIE, INT10 Group Enable Register */define((REGS16U)0x000CF4)PIEIER10 /* PIE, INT9 Group Flag Register */define ((REGS16U)0x000CF3)PIEIFR9 /* PIE, INT9 Group Enable Register */define ((REGS16U)0x000CF2)PIEIER9 /* PIE, INT8 Group Flag Register */define ((REGS16U)0x000CF1)PIEIFR8 /* PIE, INT8 Group Enable Register */define ((REGS16U)0x000CF0)PIEIER8 /* PIE, INT7 Group Flag Register */define ((REGS16U)0x000CEF)PIEIFR7 /* PIE, INT7 Group Enable Register */define ((REGS16U)0x000CEE)PIEIER7 /* PIE, INT6 Group Flag Register */define ((REGS16U)0x000CED)PIEIFR6 /* PIE, INT6 Group Enable Register */define ((REGS16U)0x000CEC)PIEIER6 /* PIE, INT5 Group Flag Register */define ((REGS16U)0x000CEB)PIEIFR5 /* PIE, INT5 Group Enable Register */define ((REGS16U)0x000CEA)PIEIER5 /* PIE, INT4 Group Flag Register */define ((REGS16U)0x000CE9)PIEIFR4 /* PIE, INT4 Group Enable Register */define ((REGS16U)0x000CE8)PIEIER4 /* PIE, INT3 Group Flag Register */define ((REGS16U)0x000CE7)PIEIFR3 /* PIE, INT3 Group Enable Register */define ((REGS16U)0x000CE6)PIEIER3 /* PIE, INT2 Group Flag Register */define ((REGS16U)0x000CE5)PIEIFR2 /* PIE, INT2 Group Enable Register */define ((REGS16U)0x000CE4)PIEIER2 /* PIE, INT1 Group Flag Register */define ((REGS16U)0x000CE3)PIEIFR1 /* PIE, INT1 Group Enable Register */define ((REGS16U)0x000CE2)PIEIER1 /* PIE, Acknowledge Register */define ((REGS16U)0x000CE1)PIEACK /* PIE, Control Register */define ((REGS16U)0x000CE0)PIECTRL /* CPUTimer 2, Prescale Register High *//**//*定義PIE配置與控制寄存器*//**/define((REGS16U)0x000C17)TIMER2TPRH /* CPUTimer 2, Prescale Register */define((REGS16U)0x000C16)TIMER2TPR /* CPUTimer 2, Control Register */define((REGS16U)0x000C14)TIMER2TCR /* CPUTimer 2, Period Register High */define((REGS16U)0x000C13)TIMER2PRDH /* CPUTimer 2, Period Register */define((REGS16U)0x000C12)TIMER2PRD /* CPUTimer 2, Counter Register High */define((REGS16U)0x000C11)TIMER2TIMH /* CPUTimer 2, Counter Register */define((REGS16U)0x000C10)TIMER2TIM /* CPUTimer 1, Prescale Register High */define((REGS16U)0x000C0F)TIMER1TPRH /* CPUTimer 1, Prescale Register */define((REGS16U)0x000C0E)T