【正文】 于FP DRAM和EDO DRAM類型Trcd [5:4] RAS 到 CAS 延時y00 = 1 clock 01 = 2 clocks10 = 3 clocks 11 = 4 clocksTcas [3] CAS 脈沖寬度0 = 1 clock 1 = 2 clocksTcp [2] CAS 預(yù)充電周期0 = 1 clock 1 = 2 clocksCAN [1:0] 列地址數(shù)目00 = 8bit 01 = 9bit10 = 10bit 11 = 11bit對于SDRAM類型Trcd [3:2] RAS 到 CAS 延時00 = 2 clocks 01 = 3 clocks 10 = 4 clocksSCAN [1:0] 列地址數(shù)目00 = 8bit 01 = 9bit 10= 10bitBANK7 BANK6 支持的存儲器類型組合 SROM DRAM SDRAM SROMSROM SDRAMDRAM SROM 不支持的組合SDRAM DRAMDRAM SDRAM3REFRESH 0x01C80024 R/W DRAM/SDRAM刷新控制寄存器 初始值0xac0000位名稱 BIT 功能REFEN [23] DRAM/SDRAM刷新允許0 = Disable 1 = Enable (self or CBR/auto refresh)TREFMD [22] DRAM/SDRAM刷新模式0 = CBR/Auto Refresh 1 = Self Refresh在selfrefresh 時, DRAM/SDRAM 控制信號被適當(dāng)電平驅(qū)動Trp [21:20] DRAM/SDRAM RAS 預(yù)充電時間DRAM :00 = clocks 01 = clocks 10 = clocks 11 = clocksSDRAM :00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = Not supportTrc [19:18] SDRAM RAS 和CAS 最小時間00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocksTchr [17:16] DRAM的CAS保持時間00 = 1 clock 01 = 2 clocks 10 = 3 clocks 11 = 4 clocksReserved [15:11] Not useRefresh Counter [10:0] DRAM/SDRAM刷新計數(shù)值刷新周期計算公式:Refresh period = (2^ 11 refresh_count+1)/MCLK us和 MCLK 是 60 MHz,refresh count如下計算refresh count = 2 ^11 + 1 = 11134BANKSIZE 0x01C80028 R/W 段尺寸寄存器 初始值為 0x0位名稱 BIT 功能SCLKEN [4] 設(shè)置為1，則SCLK僅在SDRAM存取周期產(chǎn)生，這個特征將使功耗減少，推薦設(shè)置為 1。TDI輸入：TAP控制器數(shù)據(jù)輸入信號，是測試指令和數(shù)據(jù)的串行輸入腳，必須連接一個10K上拉電阻。TMS輸入：TAP控制器模式選擇信號，控制TAP控制器的狀態(tài)次序，必須連接一個10K上拉電阻。CLKout輸出：時鐘輸出信號nTRST輸入：TAP控制器復(fù)位信號，nTRST在TAP啟動時復(fù)位TAP控制器。EXTAL1模擬輸出：RTC時鐘的晶體輸出腳。PLLCAP模擬輸入：接系統(tǒng)時鐘的環(huán)路濾波電容（700PF）。不用時必須接高（）.EXTAL0模擬輸出：系統(tǒng)時鐘內(nèi)部振蕩線路的晶體輸出腳，它是XTAL0的反轉(zhuǎn)輸出信號。OM[3:2]輸入：OM[3:2]確定時鐘模式。nRESET：復(fù)位信號，nRESET掛起程序，放S3C44B0X進(jìn)復(fù)位狀態(tài)。AVCOM輸入：ADC公共參考電壓輸入。AIN[7:0] ： ADC模擬信號輸入AREFT輸入：ADC頂參考電壓輸入。SIOCK輸入輸出：SIO時鐘信號。SIORXD輸入：SIO接收數(shù)據(jù)輸入線。IISCLK輸入輸出：IIS總線串行時鐘。IISDO輸出：IIS總線串行數(shù)據(jù)輸出信號。IICSCL輸入輸出：IIC總線時鐘線。nRTS[1:0]輸出：UART請求發(fā)送輸出信號。TxD[1:0]輸出：UART發(fā)送數(shù)據(jù)線。nXDACK[1:0]輸出：外部DMA應(yīng)答信號。EINT[7:0]輸入：外部中斷請求信號。TOUT[4:0]輸出：定時器輸出信號。VLINE輸出：LCD行信號，在一行數(shù)據(jù)左移進(jìn)LCD驅(qū)動器后有效。VFRAME輸出：LCD場信號，指示一幀的開始，在開始的第一行有效。SCKE輸出：SDRAM時鐘允許信號。DQM[3:0] 輸出：SDRAM數(shù)據(jù)屏蔽信號。nSCAS輸出：SDRAM列地址選通信號。nCAS[3:0] 輸出： 列地址選通信號。nWAIT 輸入：nWAIT請求延長當(dāng)前的總線周期，只要nWAIT為低，當(dāng)前的總線周期不能完成。 160 LQFP / 160 FBGA2 管腳描述 om[1:0]: 輸入 om[1:0]設(shè)置S3C44B0X在測試模式和確定nGCS0的總線寬度,邏輯電平在復(fù)位期間由這些管腳的上拉下拉電阻確定.00:8bit 01:16bit 10:32bit 11:Test modeADDR[24:0] 輸出: 地址總線 輸出相應(yīng)段的存儲器地址.DATA[31:0] 輸入輸出:數(shù)據(jù)總線,總線寬度可編程為8/16/32 位nGCS[7:0] 輸出:芯片選擇,.nWE 輸出 :寫允許信號,指示當(dāng)前的總線周期為寫周期.nWBE[3:0] 輸出: 寫字節(jié)允許信號nBE[3:0] 輸出:在使用SRAM情況下字節(jié)允許信號.nOE輸出 :讀允許信號,指示當(dāng)前的總線周期為讀周期.nXBREQ 輸入: nXBREQ 總線控制請求信號，允許另一個總線控制器請求控制本地總線，nXBACK信號激活指示已經(jīng)得到總線控制權(quán)。 核電壓 : I/O電壓 : V to V工作頻率: Programmable baud rates. Supports MSBjustified data formatSIO (同步串口): 1ch IISbus for audio interface with DMAbased operation. 1ch MultiMaster IICBus with interruptbased operation. 16bit Watchdog Timer Gray level: 16 gray levels Dedicated DMA for fetching image data from system memory Supports virtual screen function Supports color/monochrome/gray LCD panel 8ch multiplexed ADC. Burst transfer mode to enhance the transfer rate on the FPDRAM, EDODRAM and SDRAM.s DMA requestor: Software, 4 internal function blocks (UART, SIO, Timer, IIS), and External pins. 2 channel Bridge DMA (peripheral DMA) controller. Each channel have two internal 32byte FIFO for Rx and Tx.DMA控制器功能: Supports IrDA () Supports H/W handshaking during transmit/receive 2channel UART with DMAbased or interruptbased operation 8 external interrupt ports Alarm interrupt for CPU wakeup. Full clock feature: msec, sec, min, hour, day,week, month, year. Deadzone generation. 5ch 16bit Timer with PWM / 1ch 16bit internal timer with DMAbased or interruptbasedoperation Programmable polarity of edge and level Vectored IRQ interrupt mode to reduce interrupt latency. Wake up by EINT[7:0] or RTC alarm interrupt fromidle mode.中斷控制器 Clock can be fed selectively to each function block by software. Low power Write buffer with four depth. Pseudo LRU(Least Recently Used) Replace Algorithm. 4way set associative ID(Unified)cache with 8Kbyte.電源管理支持：Normal, Slow, Idle, and Stop mode。 1ch internal timer；Watch Dog Timer；71 general purpose I/O ports / 8ch external interrupt source； RTC with calendar function； 8ch 10bit ADC； 1ch multimaster IICBUS controller； 1ch IISBUS controller； Sync. SIO interface and Onchip clock generator with PLL.?？蛇x的internal SRAM。1產(chǎn)品預(yù)覽介 紹三星的S3C44B0X 16/32位RISC處理器被設(shè)計來為手持設(shè)備等提供一個低成本高性能的方案。S3C44B0X提供以下配置： ARM7TDMI 內(nèi)核帶有8Kcache 。LCD Controller(最大支持256色STN，使用LCD專用DMA)；2ch UART with handshake(, 16byte FIFO) / 1ch SIO； 2ch general DMAs / 2ch peripheral DMAs with external request pins； External memory controller (chip select logic, FP/ EDO/SDRAM controller)； 5ch PWM timers amp。S3C44B0X采用一種新的三星ARM CPU嵌入總線結(jié)構(gòu)SAMBA2，最大達(dá)66MHZ。系統(tǒng)管理功能： 1 Little/Big endian support. 2 Address space: 32Mbytes per each bank. (Total 256Mbyte) 3 Supports programmable 8/16/32bit data bus width for each bank. 4 Fixed bank start address and programmable bank size for 7 banks. 5 . 8 memory banks. 6 memory banks for ROM, SRAM etc. 2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM)6. Fully Programmable access cycles for all memory banks.7 Supports external wait signal to expend the bus cycle.8. Supports selfrefresh mode in DRAM/SDRAM for powerdown.9. Supports asymmetric/symmetric address of DRAM.Cache 和內(nèi)部存儲器功能: The 0/4/8 Kbytes internal SRAM using unused cache memory. Write through policy to maintain the coherence between main memory and cache content. Request data first fill techn