基于fpga的可調(diào)制脈寬調(diào)制發(fā)生器的設(shè)計(jì)-展示頁(yè)
2025-03-10 09:21本頁(yè)面
【正文】 ........................................................................... 5 方案二的設(shè)計(jì) ........................................................................................... 6 方案的選擇： ........................................................................................... 7 二 脈寬調(diào)制 FPGA 輸入設(shè)計(jì) ..................................................................................... 7 脈寬調(diào)制數(shù)值 輸入方法的設(shè)計(jì) ...................................................................... 7 方法一： ................................................................................................ 7 方法二： ................................................................................................ 7 方法一和二的選擇比較： ...................................................................... 8 VHDL 數(shù)值輸入使然模塊的設(shè)計(jì) .................................................................... 8 VHDL 使然程序設(shè)計(jì)： ............................................................................ 8 VHDL 使然軟件模塊設(shè)計(jì) ........................................................................... 9 VHDL 使然模塊波形仿真 ........................................................................ 9 VHDL 輸入數(shù)值處理模塊的設(shè)計(jì) .................................................................... 10 輸入數(shù)值處理程序設(shè)計(jì) .......................................................................... 10 VHDL 輸入數(shù)值軟件模塊設(shè)計(jì) ................................................................ 11 VHDL 數(shù)值輸入模塊軟件仿真 ................................................................. 11 相頻檢波模塊的設(shè)計(jì) ................................................................................... 12 相頻檢波模塊軟件實(shí)現(xiàn) .......................................................................... 12 相頻檢波模塊仿真 .................................................................................... 12 脈寬調(diào)制數(shù)值輸入方案仿真結(jié)果總結(jié) ......................................................... 13 VHDL 模塊的設(shè)計(jì)綜合 ............................................................................ 13 VHDL 模塊綜合仿真 ................................................................................ 14 數(shù)碼顯示管的數(shù)值顯示設(shè)計(jì) ........................................................................ 14 數(shù)碼管原理圖說(shuō)明 ............................................................................... 14 4 數(shù)碼顯 示管 VHDL 程序設(shè)計(jì) .................................................................... 15 數(shù)碼管 VHDL 顯示模塊設(shè)計(jì) .................................................................. 17 VHDL 程序仿真 ..................................................................................... 17 FPGA 下載與配置 ........................................................................................ 18 三 VHDL 脈寬調(diào) 制硬件實(shí)現(xiàn) .................................................................................... 20 FPGA 芯片選擇 ............................................................................................ 20 電路圖的設(shè)計(jì) ................................................................................................ 20 實(shí)驗(yàn)數(shù)據(jù)驗(yàn)證 ................................................................................................ 21 四、問(wèn)題及展望 ........................................................................................................ 22 五 結(jié)束語(yǔ) ............................................................................................................... 23 參考文獻(xiàn) ................................................................................................................... 24 5 一 PWM 脈
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