基本單元電路4-文庫(kù)吧資料
2024-10-13 15:52本頁(yè)面
【正文】 gnal on either the rising or falling edge of the clock). A Short Clock Pulse FlipFlop ?用與非門(mén)實(shí)現(xiàn)的 SR 觸發(fā)器 . ?這種 JK 觸發(fā)器允許 J, K同時(shí)為高 , 并且此時(shí)輸出并不相等 . ?如果時(shí)鐘保持低電平 , 輸出電平仍然保持原來(lái)鎖存的值 ?如果時(shí)鐘保持高電平 , 會(huì)發(fā)生什么 ? ?由什么決定振蕩頻率 ? ?要確保正常的鎖存操作 , 時(shí)鐘脈沖需要多短 ? A Short Clock Pulse FlipFlop ?如果時(shí)鐘保持高電平 , 會(huì)發(fā)生什么 ? ? 有書(shū)上 266 頁(yè) “ Holding the clock signal high causes the output of the FF to oscillate between a logic 0 and 1.” ?以下正確否 ? 1 1 1 1 1 1 1 1 CLK Oscillate Set Reset No Change Function 1 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 1 1 0 Q 0 0 0 J 1 0 0 K 0 1 0 0 1 0 1 1 1 0 1 1 1 0 1 Q R S Q_ Q_ Level Sensitive D FlipFlop ?當(dāng)時(shí)鐘為高電平時(shí)， D輸入的邏輯電平可以輸送到 Q輸出端 (When clock is high the logic level of the D input is passed through to the Q output) ?當(dāng)時(shí)鐘跳變成低電平 , D輸入的在時(shí)鐘高電平最后時(shí)刻的數(shù)據(jù)被鎖存到 Q輸出(When the clock transitions low, the last value on the D input is latched onto the Q output). ?時(shí)鐘為低電平時(shí) ,Q不變 (While the clock is low the Q output does not change). ?注意 :此電路不是邊沿敏感的 , 因?yàn)槌藭r(shí)鐘下降沿外 , 輸出可以隨時(shí)改變 (Note: this circuit is not edge sensitive because the output can change at times other than the falling clock edge). CLK D Q NAND 波形圖 Edge Triggered FlipFlops ? 將數(shù)據(jù)的跳變限制在時(shí)鐘的邊沿的一種策略是應(yīng)用 2個(gè)串聯(lián)的觸發(fā)器 (One strategy for limiting transitions to just the clock edge is to use 2 FlipFlops in series). ? 在這種主 從結(jié)構(gòu)中 ,主鎖存器和從鎖存器的時(shí)鐘相反 (In this MasterSlave configuration, the Master latch receives the clock and the Slave latch receives an inverted clock). ? 由于在不同的時(shí)鐘相位上工作 , 輸出并不會(huì)隨輸入變化而變化 (By operating on different phases of the clock, the output is not allowed to change with changes on the input). ? 電路的復(fù)位和允許電路可以很方便地在與非門(mén)和 SR觸發(fā)器之間加入 (Reset and Enable circuitry can
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