【正文】 ，處理器設(shè)計(jì)及制造技術(shù)一直保持著強(qiáng)勁的快速發(fā)展勢(shì)頭，其發(fā)展歷程大致遵從摩爾定律，單個(gè)芯片上所集成的電路的數(shù)目，每隔 18 個(gè)月就翻一番，如圖 111所示。CPU 按照其處理信息的字長(zhǎng)可以分為：8 位微處理器、16 位微處理器、32 位微處理器以及 64 位微處理器等等。其主要功能是進(jìn)行運(yùn)算和邏輯運(yùn)算，內(nèi)部結(jié)構(gòu)大概可以分為控制單元、算術(shù)邏輯單元和存儲(chǔ)單元等幾個(gè)部分。其中單周期CPU 基于 Altra 公司的 Cyclone III 系列 EP3C120F484C7 器件綜合的頻率可達(dá)，而多周期 CPU 的綜合頻率可達(dá) ，五級(jí)流水線 CPU 的綜合頻率可達(dá) 。在完成了各個(gè)版本的 CPU 的整體邏輯設(shè)計(jì)后，通過 Quartus II 時(shí)序仿真軟件在所設(shè)計(jì)的 CPU 上運(yùn)行了測(cè)試程序，測(cè)試輸出波形表明了處理器邏輯設(shè)計(jì)的正確性。本文的主體部分首先詳細(xì)描述了處理器各個(gè)獨(dú)立功能模塊的設(shè)計(jì)，為后續(xù)的整體設(shè)計(jì)實(shí)現(xiàn)提供邏輯功能支持。本文的首先概述了 MIPS 指令集的重要特征，為討論 CPU 的具體設(shè)計(jì)奠定基礎(chǔ)。本文在詳細(xì)研究 32 位 MIPS 處理器體系結(jié)構(gòu)的基礎(chǔ)之上，在 Quartus II 環(huán)境中，完全依靠自己的研發(fā)設(shè)計(jì)能力，采用硬件描述語(yǔ)言 VHDL 完成了擁有自主知識(shí)產(chǎn)權(quán)的基于 MIPS 指令集的 32 位 RISC 處理器的邏輯設(shè)計(jì)。MIPS 是世界上很流行的一種 RISC處理器。本 科 生 畢 業(yè) 論 文題 目： 基于 MIPS 指令集的 32 位 RISC 處理器邏輯設(shè)計(jì) 院 系： 信息科學(xué)與技術(shù)學(xué)院 專 業(yè)： 計(jì)算機(jī)科學(xué)與技術(shù) 學(xué)生姓名： 李瑋超 學(xué) 號(hào)： 05373024 指導(dǎo)教師： 李國(guó)楨 副教授 二〇〇九 年 四 月 i 摘 要CPU 是計(jì)算機(jī)系統(tǒng)的核心部件，在各類信息終端中得到了廣泛的應(yīng)用。處理器的設(shè)計(jì)及制造技術(shù)也是計(jì)算機(jī)技術(shù)的核心之一。MIPS 的意思是“ 無(wú)內(nèi)部互鎖流水級(jí)的微處理器” （Microprocessor without interlocked piped stages） ，其機(jī)制是盡量利用軟件辦法避免流水線中的數(shù)據(jù)相關(guān)問題。共開發(fā)出單周期、多周期、五級(jí)流水線等 3 個(gè)不同版本的 32 位 RISC 處理器，均通過 Quartus II 進(jìn)行了時(shí)序仿真和性能比較分析。本文設(shè)計(jì)的 3 個(gè)版本的 CPU 均實(shí)現(xiàn)了一個(gè)共包含 59 條指令的 32 位 MIPS 指令子集。隨后按照單周期、多周期、流水線的順序，循序漸進(jìn)的圍繞著指令執(zhí)行過程中需經(jīng)歷的五個(gè)階段，詳細(xì)描述了 3 個(gè)版本的處理器中各階段的邏輯設(shè)計(jì)。本文還通過 Quartus II 中的 Quartus II Time Quest Timing Analyzer 軟件，基于 Altra 公司的 FPGA 器件比較分析了所設(shè)計(jì)的 3 個(gè)版本 CPU 的性能。關(guān)鍵詞： MIPS，處理器，單周期，多周期，流水線，VHDL ii iii AbstractCPU is a core ponent of puter system, which has been widely used in a variety of information devices in different areas of industry. Processor design and manufacturing technology is also one of the most important puter technologies nowadays. MIPS is one of the worldwide popular RISC processor. MIPS means “microprocessor without interlocked piped stages”. Its mechanism is to make full use of software to solve the datarelated problem in the pipeline. Based on a detailed study of MIPS instruction set architecture, this paper describes the logic design of a MIPSbased 32bit RISC processor in detail, which is developed with hardware description language VHDL in Quartus II . The design includes the following three versions of 32bit RISC processor, the singlecycle version, the multicycle version and the 5pipeline version. All the three versions have been tested in the Quartus II timing simulation software environment. A performance analysis of the three versions is given by the paper according to the timing simulation test results. First of all, the paper provides an overview of the important features of the MIPS instruction set, including the instruction format, instruction classification and the addressing mode, which lays the foundation of the following discussion about the specific logic design. A 59instruction subset of 32bit MIPS instruction set has been implemented on all of the three processor versions discussed in the paper.The main body of the paper first describes in detail the logic design of the independent functional modules in the processors, providing functional support for the followup overall design. Next, the article describes the most important logic designs of the five instruction execution stages of the three processor versions, in accordance with the stepbystep sequence of the singlecycle version, the multicycle version and the 5pipeline version. Upon the pletion of the overall logic design of each processor version, the correctness of the logic design is proved by the waveform output of timing simulation in Quartus II Timing Simulation Software. iv The paper also gives a parative performance analysis of the three processor versions according to the analysis data of Quartus II Time Quest Timing Analyzer. Based on the Altra Cyclone III series EP3C120F4847 FPGA device, the instruction execution frequency of the singlecycle processor is MHz, while the multicycle processor’s is MHz and the 5pipeline processor’s is MHz.Keywords: MIPS, CPU, singlecycle, multicycle, pipeline, VHDL v 目 錄第一章 緒論 ................................................................................................................................................1 處理器概述 .................................................................................................................1 處理器的設(shè)計(jì)過程與目標(biāo) .........................................................................................2 處理器的設(shè)計(jì)過程 ...........................................................................................2 處理器的設(shè)計(jì)目標(biāo) ...........................................................................................2 本文的主要成果 .........................................................................................................3 本文章節(jié)說明 .............................................................................................................4第二章 MIPS 體系結(jié)構(gòu)概述 .......................................................................................................................5 復(fù)雜指令集與精簡(jiǎn)指令集的比較 .............................................................................5 MIPS 處理器簡(jiǎn)介 ........................................................................................................6 MIPS 體系結(jié)構(gòu)概述 ....................................................................................................7 MIPS 指令集簡(jiǎn)介 ..............................................................................................7 基于 MIPS 指令集進(jìn)行設(shè)計(jì)的原因 ...............................................................12 本設(shè)計(jì)實(shí)現(xiàn)的指令集系統(tǒng) .......................................................................................12第三章 處理器獨(dú)立功能模塊的設(shè)計(jì) ......................................................................................................16 輔助邏輯模塊的設(shè)計(jì) ...............................................................................................16 譯碼器 .............................................................................................................16