英語,i2c總線規(guī)范21部分-文庫吧資料
2024-08-29 17:05本頁面
【正文】 uence and has to switch its internal circuit from the Fastmode setting to the Hsmode setting. Between times t1 and tH the connected master and slave devices perform this switching by the following actions.The active (winning) master:1. Adapts its SDAH and SCLH input filters according to the spike suppression requirement in Hsmode.2. Adapts the setup and hold times according to the Hsmode requirements.3. Adapts the slope control of its SDAH and SCLH output stages according to the Hsmode requirement.4. Switches to the Hsmode bitrate, which is required after time tH.5. Enables the current source pullup circuit of its SCLH output stage at time tH. The nonactive, or losing masters:1. Adapt their SDAH and SCLH input filters according to the spike suppression requirement in Hsmode.2. Wait for a STOP condition to detect when the bus is free again. All slaves:1. Adapt their SDAH and SCLH input filters according to the spike suppression requirement in Hsmode.2. Adapt the setup and hold times according to the Hsmode requirements. This requirement may already be fulfilled by the adaptation of the input filters.3. Adapt the slope control of their SDAH output stages, if necessary. For slave devices, slope control is applicable for the SDAH output stage only and, depending on circuit tolerances, both the Fast and Hsmode requirements may be fulfilled without switching its internal circuit.At time tFS in , each connected device must recognize the STOP condition (P) and switch its internal circuit from the Hsmode setting back to the Fastmode setting as present before time t1. This must be pleted within the minimum bus free time as specified in Table 5 according to the Fastmode specification. Hsmode devices at lower speed modesHsmode devices are fully downwards patible, and can be connected to an F/Smode I2Cbus system (see ). As no master code will be transmitted in such a configuration, all Hsmode master devices stay in F/Smode and municate at F/Smode speeds with their currentsource disabled. The SDAH and SCLH pins are used to connect to the F/Smode bus system, allowing the SDA and SCL pins (if present) on the Hsmode master device to be used for other functions. Hsmode devices at F/Smode speed(1) Bridge not used. SDA and SCL may have an alternative function.(2) To input filter.(3) The currentsource pullup circuit stays disabled.(4) Dotted transistors are optional opendrain outputs which can stretch the serial clock signal SCL. Mixed speed modes on one serial bus systemIf a system has a bination of Hs, Fast and/or Standardmode devices, it’s possible, by using an interconnection bridge, to have different bit rates between different devices (see Figs 24 and 25).One bridge is required to connect/disconnect an Hsmode section to/from an F/Smode section at the appropriate time. This bridge includes a level shift function that allows devices with different supply voltages to be connected. For example F/Smode devices with a VDD2 of 5 V can be connected to Hsmode devices with a VDD1 of 3 V or less (. where VDD2 179。 The output buffers of Hsmode devices incorporate slope control of the falling edges of the SDAH and SCLH signals.Figure 20 shows the physical I2Cbus configuration in a system with only Hsmode devices. Pins SDA and SCL on the master devices are only used in mixedspeed bus systems and are not connected in an Hsmode only system. In such cases, these pins can be used for otherfunctions.Optional series resistors Rs protect the I/O stages of the I2Cbus devices from highvoltage spikes on the bus lines and minimize ringing and interference.Pullup resistors Rp maintain the SDAH and SCLH lines at a HIGH level when the bus is free and ensure the signals are pulled up from a LOW to a HIGH level within the required rise time. For higher capacitive busline loads (100 pF), the resistor Rp can be replaced by external current source pullups to meet the rise time requirements. Unless proceeded by an acknowledg
數(shù)學(xué)相關(guān)推薦
鄂ICP備17016276號-1