51系列單片機(jī)中英文翻譯資料-文庫(kù)吧資料
2024-11-11 05:34本頁(yè)面
【正文】 e is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS51 series onechip puter and general puter disposes the way in addition. General puter for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three abovementioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. 8051 onechip puter have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate twoway mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these selfsame. Expand among the system of memory outside having slice, four port these may serve as accurate twoway mouth of I/O in mon use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off。 作為在 Q=1時(shí) ,信號(hào)線可以生產(chǎn) W. 節(jié)目時(shí) ,它是第一個(gè)功能 ,但仍是第二個(gè)功能不用軟 件 P3 口提前成立 . 這不是硬件是在自動(dòng)有兩個(gè)功能 outputted 當(dāng) CPU 進(jìn)行社會(huì)主義和尋求地點(diǎn) (所在地或字節(jié) )訪 P3 口 /不是在持久排隊(duì) ,有在硬件門閂促使 = 經(jīng)營(yíng)原則 P3 口類似于 P1 口 . 生產(chǎn)級(jí)的 P3 口 ,P1,P1,內(nèi)有連接負(fù)載阻力劃 ,每個(gè)人可以帶動(dòng) 4 產(chǎn)出模型LSTTL 載荷 . 而作為輸入口 ,任何 NMOS 電路可驅(qū)動(dòng) TTL或 P1 的 8051 一個(gè)電腦芯片 P3 口的正常發(fā)展 . 由于產(chǎn)量等作出抵抗的人 ,也可以公開方式收藏或流失的根源就是反抗的方式 ,要求公開 ,不須具備抵抗繪畫 . 別人都準(zhǔn)確雙向口也 . 當(dāng)行為投入 ,要 寫出一首相應(yīng)的港口與門閂 . 以 80c51 一個(gè)計(jì)算機(jī)芯片 ,只能提供港口毫安的電流電產(chǎn)出 ,它是生產(chǎn)口去要求一個(gè)普通的計(jì)算是將晶體管、接觸的阻力應(yīng)該在港口及半導(dǎo)體基地 同時(shí)為了抑制高電力輸出 P1~P3 級(jí)是恢復(fù)王位是一個(gè)著手運(yùn)作一個(gè)計(jì)算機(jī)芯片 . 其主要功能是將電腦變成 0000h 開始 ,使一個(gè)開始進(jìn)行計(jì)算機(jī)芯片進(jìn)行程序 0000h 單位 . 除了那些進(jìn)入正常 initialized 系統(tǒng) ,因?yàn)樗某绦虿僮魇д`或操作失誤不多 ,為了擺脫困境 ,必須按國(guó)家和恢復(fù)王位 ,恢復(fù)太重要了 . 這是一項(xiàng)投入恢復(fù)王位 ,結(jié)束了在 8051 年中國(guó)信息表寄 . 恢復(fù)王位高有效信號(hào) ,應(yīng)保持 24 震撼周期 (機(jī)器周期 ,2)有效時(shí)間段 . 6 如果使用頻率前去輝煌 ,恢復(fù)王位信號(hào)完成期限不得超過(guò) 4 微妙的王位 ,恢復(fù)營(yíng)業(yè) . 邏輯電路生產(chǎn)情況 ,恢復(fù)王位的信號(hào) : 恢復(fù)王位的電路兩部分組成 ,包括外部的芯片完全 . 外界產(chǎn)生電路恢復(fù)王位信號(hào)(表 )交給史密特的啟動(dòng) ,恢復(fù)王位樣品電路產(chǎn)量 ,史密特觸發(fā)不斷每一 s5p機(jī)器周期有一次 ,光有與恢復(fù)王位和經(jīng)營(yíng)所需 insidly 信號(hào) . 恢復(fù)王位抵抗一般線路、電容參數(shù)適合 6精彩震撼 ,是否能恢復(fù)王位高信號(hào)機(jī)會(huì)大于 2 周期保證 . 正
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