【正文】 個(gè)簽名字節(jié)地址為 030H031H 和 032H 于聲明該器件的廠商號(hào)和編程電壓讀簽名字節(jié)的過程和單元 030H031H 和 032H 的正常校驗(yàn)相仿只需要將 P36 和 P37 保持低電平返回值意義如下 030H 1EH 聲明產(chǎn)品由 ATMEL 公司制造 031H 51H 聲明為 89C51 單片機(jī) 032H FFH 聲明為 12V 編程電壓 032H 05H 聲明為 5 編程電壓 24 編程接口 采用控制信號(hào)的正確組合可對(duì) Flash 閃速存儲(chǔ)陣列中的每一代碼字節(jié)進(jìn)行寫入和存儲(chǔ)器的整片擦除寫操作周期是自身定時(shí)的初始化后它將自動(dòng)定時(shí)到操作完成微機(jī)接口實(shí)現(xiàn)兩種信息形式的交換在計(jì)算機(jī)之外由電子系統(tǒng)所處理的信息以一種物理信號(hào)形式存在但在程序中它是用數(shù)字表示的任一接口的功能都可分為以某種形式進(jìn)行數(shù)據(jù)庫(kù)變換的一些操作所以外部和內(nèi)部形式的轉(zhuǎn)換是由許多步驟完成的模擬 數(shù)字轉(zhuǎn)換器 ADC 用來將連續(xù)變化信號(hào)變成相應(yīng)的數(shù)字量這數(shù)字量可是可能性的二進(jìn)制數(shù)值中的一固定值如果傳感器輸出不是連續(xù)變化的就不需模擬 數(shù)字轉(zhuǎn)換這種情況下信號(hào)調(diào)理單元必須將輸入信號(hào)變換成為另一信 號(hào)也可直接與接口的下一部分即微計(jì)算機(jī)本身的輸入輸出單元相連接輸出接口采用相似的形式明顯的差別在于信息流的方向相反是從程序到外部世界這種情況下程序可稱為輸出程序它監(jiān)督接口的操作并完成數(shù)字 模擬轉(zhuǎn)換器 DAC 所需數(shù)字的標(biāo)定該子程序依次送出信息給輸出器件產(chǎn)生相應(yīng)的電信號(hào)由 DAC 轉(zhuǎn)換成模擬形式最后信號(hào)經(jīng)調(diào)理通常是放大以形成適應(yīng)于執(zhí)行器操作的形式在微機(jī)電路中使用的信號(hào)幾乎總是太小而不能被直接地連到外部世界因而必須用某種形式將其轉(zhuǎn)換成更適宜的形式接口電路部分的設(shè)計(jì)是使用微機(jī)的工程師所面臨最重要的任務(wù)之一我們已經(jīng)了解到微 機(jī)中信號(hào)以離散的位形式表示當(dāng)微機(jī)要與只有打開或關(guān)閉操作的設(shè)備相連時(shí)這種數(shù)字形式是最有用的這里每一位都可表示一開關(guān)或執(zhí)行器的狀態(tài)為了解決實(shí)際問題一個(gè)單片機(jī)不僅包括 CPU 程序和數(shù)據(jù)存儲(chǔ)器另外它必須含有通過 CPU 訪問外部信息的硬件一旦 CPU 收集到數(shù)據(jù)信息和流程它必須能夠改變外部領(lǐng)域的一部分這些硬件設(shè)備稱作外圍設(shè)備它們是 CPU 通往外部的窗口 單片機(jī)可利用外圍設(shè)備中最基本的用于一般用途的 IO 接口每個(gè) IO 接口既可作為輸入端又可作為輸出端每個(gè) IO 接口的功能取決與程序初始化階段對(duì)數(shù)據(jù)方位寄存器相應(yīng)位進(jìn)行置一和清 零操作通過 CPU 指令對(duì)數(shù)據(jù)寄存器相應(yīng)位進(jìn)行置一和清零來置一和清零輸出端口同樣輸入端口邏輯位也可以通過 CPU 指令訪問一些類型的串行口單元允許 CPU 與外部設(shè)備進(jìn)行串口通信用串口位代替平行位進(jìn)行通信需要少許的 IO 口這樣使通信費(fèi)用降低但速度也相對(duì)慢些串口傳送可以同步也可以異步 The General Situation of AT89C51 Chapter 1 The application of AT89C51 Microcontrollers are used in a multitude of mercial applications such as modems motorcontrol systems air conditioner control systems automotive engine and among others The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such highspeed eventbased applications However these critical application domains also require that these microcontrollers are highly reliable The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the ponent and at the system level Intel Plaform Engineering department developed an objectoriented multithreaded test environment for the validation of its AT89C51 automotive microcontrollers The goals of thisenvironment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers The environment was developed in conjunction with Microsoft Foundation Classes AT89C51 The paper describes the design and mechanism of this test environment its interactions with various hardwaresoftware environmental ponents and how to use AT89C51 11 Introduction The 8bit AT89C51 CHMOS microcontrollers are designed to handle highspeedcalculations and fast inputoutput operations MCS 51 microcontrollers are typically used for highspeed event control systems Commercial applications include modemsmotorcontrol systems printers photocopiers air conditioner control systems disk drivesand medical instruments The automotive industry use MCS 51 microcontrollers in enginecontrol systems airbags suspension systems and antilock braking systems ABS The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced onchip peripheral functions set such as automotive powertrain control vehicle dynamic suspension antilock braking and stability control applications Because of these critical applications the market requires a reliable costeffective controller with a low interrupt latency response ability to service the high number of time and event driven integrated peripherals needed in real time applications and a CPU with above average processing power in a single package The financial and legal risk of having devices that operate unpredictably is very high Once in the market particularly in mission criticalapplications such as an autopilot or antilock braking system mistakes are financiallyprohibitive Redesign costs can run as high as a 500K much more if the fix means 2 back annotating it across a product family that share the same core andor peripheral design flaw In addition field replacements of ponents is extremely expensive as the devices are typically sealed in modules with a total value several times that of the ponent To mitigate these problems it is essential that prehensive testing of the controllers be carried out at both the ponent level and system level under worst case environmental and voltage conditionsThis plete and thorough validation necessitates not only a welldefined pro