【正文】 e t 3 : a n d 1 , i n p o r t 3 。n e t 2 : a n d 1 , i n p o r t 2 。n e t 1 : a n d 1 , i n p o r t 1 。i n st a n ce s: a n d 1 , a n d 2 , a n d 3 , a n d 4 , a n d 5 , o r 1 , i n v2 ,in v3 , i n v4 。 2022 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Synthesis After the simulation, the puter program optimizes the logic by eliminating redundant terms and generating a list, (a connection list) that is a plete description of the circuit. SynthesisZA1A0A2A3n e t 1n e t 2n e t 3n e t 4and1n e t 5n e t 6n e t 7n e t 9and2n e t 1 0n e t 8n e t 1 1in v1n e t 1 4and3n e t 1 5n e t 1 3n e t 1 2n e t 1 6in v2n e t 1 7and4n e t 2 0n e t 1 9n e t 1 8n e t 2 1in v3n e t 2 3n e t 2 5n e t 2 4and5in v4n e t 2 2I1I2I3I4o r 1n e t 2 6O1N e t l i st ( L o g i c3 )n e t n a m e : i n st a n ce n a m e , f r o m 。 Entity section Architecture section Input and output variable names and types Assigns expression on right to variable on left Boolean descriptions of circuit } ABSR N o tDesign entrySchematicHDL169。 QNot = not B or not Q。 end entity S_RLatch。 2022 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Programmable Logic Software entity S_RLatch is port (A, B: in bit。 Design entrySchematicHDL169。 2022 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Programmable Logic Software In schematic entry, the design is drawn on a puter screen by placing ponents and connecting then with simulated wires. You do not need to know the details of an HDL. After drawing the schematic, it can be reduced to a single block symbol: Design entrySchematicHDL169。 2022 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary FPGAs Logic modules can be configured for binational logic, registered logic, or a bination of both. The global interconnects distribute signals (including the clock) to various CLBs. FPGAs may also have a hard core portion of logic that is put in by the manufacturer and cannot be reprogrammed by the user. These FPGAs are useful in monly used functions such as I/O interfaces. C L BL o g i c m o d u l eL o ca li n t e r co n n e ctG l o b a l co l u m ni n t e r co n n e ctL o g i c m o d u l eL o g i c m o d u l eL o g i c m o d u l eC L BL o g i c m o d u l eL o ca li n t e r co n n e ctL o g i c m o d u l eL o g i c m o d u l eL o g i c m o d u l eG l o b a l r o wi n t e r co n n e ct169。 2022 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Macrocells In addition to bination logic, some macrocells have registered outputs available (using programmable flipflops). This allows the CPLD to perform sequential logic. 1 5 e xp a n d e r p r o d u ctt e r m s f r o m o t h e rm a cr o ce l l s3 6 l i n e sf r o m P I AS h a r e de xp a n d e rP a r a l l e l e xp a n d e r sf r o m o t h e rm a cr o ce l l sT o I / OP r o d u ct t e r mse l e ct i o nm a t r i xD / TCENP R EC L RQM U X 1M U X 2M U X 3VCCM U X 4M U X 5F r o mI/OG l o b a lcl e a rG l o b a lcl o ck169。 1 6 3616I/Oco n t r o lb l o ckL o g i c a r r a y b l o ck( L A B A )3616I/Oco n t r o lb l o ckM a cr o ce l l 1M a cr o ce l l 2M a cr o ce l l 1 6L o g i c a r r a y b l o ck( L A B B )M a cr o ce l l 1M a cr o ce l l 2M a cr o ce l l 1 68 1 68 1 6P I A169。 2022 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary CPLDs A plex programmable logic device (CPLD) has multiple logic array blocks (LABs) that are actually SPLDs on a single IC. LABs are connected via a programmable interconnect array (PIA). Various CPLDs have different structures for these elements. I/OP I AI/OI/O I/OI/O I/OL o g i c a r r a yb l o ck ( L A B )S P L DL o g i c a r r a yb l o ck ( L A B )S P L DL o g i c a r r a yb l o ck ( L A B )S P L DL o g i c a r r a yb l o ck ( L A B )S P L DL o g i c a r r a yb l o ck ( L A B )S P L DL o g i c a r r a yb l o ck ( L A B )S P L DThe PIA is the interconnection between the LABs. Logic is fitted to the CPLD and routing is determined by a highlevel programming lang