【正文】 0. E. Periodic Interrupt Flag (PF) bit is cleared to 0. F. The device is not accessible until RESET is returned high. G. Alarm Interrupt Flag (AF) bit is cleared to 0. H. IRQ pin is in the high impedance state. I. Square Wave Output Enable ( SQWE ) bit is cleared to 0. J. Update Ended Interrupt Enable (UIE) is cleared to 0. In a typical application RESET can be connected to VCC. This connection will allow the DS12887 to go in and out of power fail without affecting any of the control registers. TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate memory bytes. The time, calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the 10 time, calendar, and alarm bytes can be either Binary or Binary–Coded Decimal (BCD) format. Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a ogic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 10 time, calendar, and alarm registers in a selected format (binary or BCD), th。 蘇州大學(xué)本科生畢業(yè)論文（設(shè)計） 21 英文資料 DS12887 FEATURES ?? Drop–in replacement for IBM AT puter clock/calendar ?? Pinpatible with the MC146818B and DS1287 ?? Totally nonvolatile with over 10 years of operation in the absence of power ?? Self–contained subsystem includes lithium, quartz, and support circuitry ?? Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year pensation valid up to 2100 ?? Binary or BCD representation of time, calendar, and alarm ?? 12– or 24–hour clock with AM and PM in12–hour mode ?? Daylight Savings Time option ?? Selectable between Motorola and Intel bus timing ?? Multiplex bus for pin efficiency ?? Interfaced with software as 128 RAM locations – 14 bytes of clock and control registers – 114 bytes of general purpose RAM ?? Programmable square wave output signal ?? Bus–patible interrupt signals (IRQ ) ?? Three interrupts are separately software–maskable and testable – Time–of–day alarm once/second to once/day – Periodic rates from 122 ms to 500 ms – End of clock update cycle 蘇州大學(xué)本科生畢業(yè)論文（設(shè)計） 22 PIN DESCRIPTION AD0–AD7 – Multiplexed Address/Data Bus NC – No Connection MOT – Bus Type Selection CS – Chip Select AS – Address Strobe R/ W – Read/Write Input DS – Data Strobe RESET – Reset Input IRQ – Interrupt Request Output SQW – Square Wave Output VCC – +5 Volt Supply GND – Ground DESCRIPTION The DS12887 Real Time Clock plus RAM is designed to be a direct replacement for the DS1287. The DS12887 is identical in form, fit, and function to the DS1287, and has an additional 64 bytes of general purpose RAM. Access to this additional RAM space is determined by the logic level presented on AD6 during the address portion of an access cycle. A lithium energy source, quartz crystal, and write– protection circuitry are contained within a 24–pin dual inline package. As such, the DS12887 is a plete subsystem replacing 16 ponents in a typical application. The functions include a nonvolatile time–of–day clock, an alarm, a onehundred–year calendar, programmable interrupt, square wave generator, and 114 bytes of nonvolatile static RAM. The real time clock is distinctive in that time–of–day and memory are maintained even in the absence of power. 蘇州大學(xué)本科生畢業(yè)論文（設(shè)計） 23 OPERATION The block diagram in F igure 1 shows the pin connections with the major internal functions of the DS12887. The following paragraphs describe the function of each pin. BLOCK DIAGRAM DS12887 Figure 1 POWER–DOWN/POWER–UP CONSIDERATIONS The Real Time Clock function will continue to operate and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile 電源開關(guān)和寫保護 蘇州大學(xué)本科生畢業(yè)論文（設(shè)計） 24 regardless of the level of the VCC input. When VCC is applied to the DS12887 and reaches a level of greater than volts, the device bees accessible after 200 ms, provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A). This time period allows the system to stabilize after power is applied. When VCC falls below volts, the chip select input is internally forced to an inactive level regardless of the value of CS at the input pin. The DS12887 is, therefore, write–protected. When the DS12887 is in a write–protected state, all inputs are ignored and all outputs are in a high impedance state. When VCC falls below a level of approximate ly 3 volts, the external VCC supply is switched off and an internal lithium energy source supplies power to the Real Time Clock and the RAM memory. SIGNAL DESCRIPTIONS GND, VCC – DC power is provided to the device on these pins. VCC is the +5 volt input. When 5 volts are applied within normal limits, the device is fully accessible and data can be written and read. When VCC is below volts typical, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below 3 volts typical, the RAM and timekeeper are switched over to an internal lithium energy source. The timekeeping function maintains an accuracy of 177。正 是有了他們的悉心幫助和支持，才使我的畢業(yè)論文工作順利完成 。在此向老師表示深深的感謝和崇高的敬意。由于未使用電感，可不受磁場的干擾，因此抗干擾能力強、能與 PIN 光電二極管直接連接、 集電極開路輸出，能直接驅(qū)動 TTL 或 COMS 電路 等優(yōu) 點。 該設(shè)計有 優(yōu)點很多 優(yōu)點： 總體電路簡潔明了， 本電路采用 555 時基電路組成的多諧振蕩器，具有定時精度高、負載能力強、通用信好、工 作可靠、使用方便、價格低廉 等特點。當(dāng)然，這些都離不開老師平時的細心輔導(dǎo)。 只有身體力行， 按部就班，才能設(shè)計出理想的電路。希望這次的經(jīng)歷能讓我在以后學(xué)習(xí)中激勵我繼續(xù)進步。遇到問題首先要心態(tài)平衡，然后根據(jù)問題