【正文】 eneric RAMs. CS (Chip Select Input) – The Chip Select signal must be asserted low for a bus cycle in the DS12887 to be accessed. CS must be kept in the active state during DS and AS for Motorola timing and during RD and WR for Intel timing. Bus cycles which take place without asserting CS will latch addresses but no access will occur. When VCC is below volts, the DS12887 internally inhibits access cycles by internally disabling the CS input. This action protects both the real time clock data and RAM data during power outages. IRQ (Interrupt Request Output) – The IRQ pin is an active low output of the DS12887 that can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt–enable bit is set. To clear the IRQ pin the processor program normally reads the C register. The RESET pin also clears pending interrupts. When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an external pull up resistor. RESET (Reset Input) – The RESET pin has no effect on the clock, calendar, or RAM. On power–up the RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of time that RESET is held low is dependent on the application. However, if RESET is used on power–up, the time RESET is low should exceed 200 ms to make sure that the internal timer that controls the DS12887 on powerup has timed out. When RESET is low and VCC is above volts, the following occurs: A. Periodic Interrupt Enable (PEI) bit is cleared to 0. B. Alarm Interrupt Enable (AIE) bit is cleared to 0. C. Update Ended Interrupt Flag (UF) bit is cleared to 0. 蘇州大學本科生畢業(yè)論文（設計） 28 D. Interrupt Request Status Flag (IRQF) bit is cleared to 0. E. Periodic Interrupt Flag (PF) bit is cleared to 0. F. The device is not accessible until RESET is returned high. G. Alarm Interrupt Flag (AF) bit is cleared to 0. H. IRQ pin is in the high impedance state. I. Square Wave Output Enable ( SQWE ) bit is cleared to 0. J. Update Ended Interrupt Enable (UIE) is cleared to 0. In a typical application RESET can be connected to VCC. This connection will allow the DS12887 to go in and out of power fail without affecting any of the control registers. TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate memory bytes. The time, calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the 10 time, calendar, and alarm bytes can be either Binary or Binary–Coded Decimal (BCD) format. Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a ogic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 10 time, calendar, and alarm registers in a selected format (binary or BCD), th。 蘇州大學本科生畢業(yè)論文（設計） 21 英文資料 DS12887 FEATURES ?? Drop–in replacement for IBM AT puter clock/calendar ?? Pinpatible with the MC146818B and DS1287 ?? Totally nonvolatile with over 10 years of operation in the absence of power ?? Self–contained subsystem includes lithium, quartz, and support circuitry ?? Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year pensation valid up to 2100 ?? Binary or BCD representation of time, calendar, and alarm ?? 12– or 24–hour clock with AM and PM in12–hour mode ?? Daylight Savings Time option ?? Selectable between Motorola and Intel bus timing ?? Multiplex bus for pin efficiency ?? Interfaced with software as 128 RAM locations – 14 bytes of clock and control registers – 114 bytes of general purpose RAM ?? Programmable square wave output signal ?? Bus–patible interrupt signals (IRQ ) ?? Three interrupts are separately software–maskable and testable – Time–of–day alarm once/second to once/day – Periodic rates from 122 ms to 500 ms – End of clock update cycle 蘇州大學本科生畢業(yè)論文（設計） 22 PIN DESCRIPTION AD0–AD7 – Multiplexed Address/Data Bus NC – No Connection MOT – Bus Type Selection CS – Chip Select AS – Address Strobe R/ W – Read/Write Input DS – Data Strobe RESET – Reset Input IRQ – Interrupt Request Output SQW – Square Wave Output VCC – +5 Volt Supply GND – Ground DESCRIPTION The DS12887 Real Time Clock plus RAM is designed to be a direct replacement for the DS1287. The DS12887 is identical in form, fit, and function to the DS1287, and has an additional 64 bytes of general purpose RAM. Access to this additional RAM space is determined by the logic level presented on AD6 during the address portion of an access cycle. A lithium energy source, quartz crystal, and write– protection circuitry are contained within a 24–pin dual inline package. As such, the DS12887 is a plete subsystem replacing 16 ponents in a typical application. The functions include a nonvolatile time–of–day clock, an alarm, a onehundred–year calendar, programmable interrupt, square wave generator, and 114 bytes of nonvolatile static RAM. The real time clock is distinctive in that time–of–day and memory are maintained even in the absence of power. 蘇州大學本科生畢業(yè)論文（設計） 23 OPERATION The block diagram in F igure 1 shows the pin connections with the major internal functions of the DS12887. The following paragraphs describe the function of each pin. BLOCK DIAGRAM DS12887 Figure 1 POW