【正文】 sters, R0 through R7, are visible to the puter programmer. The second 8 registers, R8 though R15 , are used as temporary storage for the microprogram operands and are hidden from the programmer. Figure 103 provides a map of the expanded register file with the temporary registers shaded. As indicated previously, register R0 supplies the constant 0. registers R1 through R7 are available to the programmer for use, and registers R8 through R15 provide general temporary storage for use by microprograms, the last four registers, R12 though R15, have special uses: to keep the microcode simple, standard locations are essential for storing the operands and addresses used by execution microcode for most instructions. thus ,R12 is the location for the source address(SA), R13 for the source data (SD), R14 for the destination address(DA), and R15 for the destination data(DD). We cannot access the eight temporary registers based on the 3bit register address available in the instruction. To deal with this problem, we provide, first, 4bit register address from the microinstruction, and second, a microinstruction bit to choose between these addresses and those from the instruction. In addition, the flexibility to allow the register addressed by DST to be a source and by SRC to be a destination is needed to permit results of operations to be placed directly in memory. To acplish these goals, we modify the register file by adding the logic shown in Figure 104(a). the instruction set architecture uses two addresses, one for a source a operand and the other for the other source as well as the destination. The register file uses the B address for a source, and the A and D addresses on the file are connected together, giving the same address for the other source and the destination. Although this reduction from three to two addresses is not essential at the mincroinstruction 15 level, it decrease the number of bits needed for register addresses in the microinstruction and matches the use of the register fields in the instruction formats. A quad 2to1 multiplexer is attached to each of the two address inputs to the register file, to select between an address from the microinstruction and an address from the instruction. There is a 5bit field in the microinstruction for the bined destination and source address DSA, in addition to a 5bit field for the B address SB. The first bit of each of the these fields selects between the register file address in the microinstruction(0) and the register file address in the instruction(1). If an instruction address is selected, whether it is DST or SRC is determined by an additional quad 2to1 multiplexer. This multiplexer is controlled by the second bit of the DSA or SB fields, depending on which of them has 1 in the first bit in any microinstruction, thereby ensuring that the proper second bit is used to determine the register address. A 0 is appended to the left of the 3bit fields DST and SRC to cause them to address R0 through R7. the addition to the first bit, which selects the address source, the addresses from the microinstruction contain four bits so that all 16 registers can be reached. The final change to the register file is to replace the storage elements for R0 in the file with open circuits on the lines that were their inputs and with constant zero valves on the lines that were their outputs. A symbol for the resulting register file is show in Figure 104(b). We find that, based on the eight shift instructions provided, the shifter from section 810, needs to be modified. The modifications involve the end bits of the shift logic. For logical shifts, a 0 is inserted, as before. For the right arithmetic shift, she sign bit is the ining bit, and for the left arithmetic shift, 0 is the ining bit. Rotates require that the bit from the opposite end of the shifter be fed around. Finally, rotates with carry require that the carry flipflop output be provide as an input on both ends of the shifter. The inputs are furnished by two 4t01 multiplexers, MUX R and MUX L, added to a basic 16bit shifter, all shown in Figure 105(a). also, the appropriate end bits from the input operand must be sent to the carry flipflop. A 2to1 multiplexer MUX SO selects the end bit to pass to the carry flipflop C. the symbol for the new shifter, which replaces the basic shifter from section 810, appears in Figure 105(b), FS3, FS2, FS1, and FS0 from the FS field drive the control inputs S3, S2, S1 and S0, respectively. All modifications to the original datapath are represented in Figure 106. As a part of the design process, the new datapath needs to be checked to make sure that it has all of the capabilities necessary for implementing the instruction set and addressing modes .Certainly ,some decisions have been made that have not been discussed. For example, there is no dedicated multiplication or division hardware, so these operations must be implemented by microprograms controlling the datapath. 16 Microprogrammed Control Organization The microgrammed control unit acpanies the datapath of Figure 106 in Figure 107. The control consists of four principal parts. One is the control unit registers : the instruction register IR, the program counter PC, and the stack pointer SP. In some designs the PC and SP are logically included in the register file and thus are a part of the datapath .Here, since they are separate from the register file and are used primarily for program control ,we haveincluded them with the control . Sequencing within the control unit is provides by the microsequencer , which contains two registers: the control address register CAR and the subroutine branch register SBR. The program counter for the microprogram , the CAR simply counts up to the next address in sequence or loads in parallel . With a parallel load , the