【正文】 However, sometimes it is meant to refer to the entire system except for the crystal and VCO. This is because these ponents are difficult to integrate on a PLL synthesizer chip. The transfer function from the output of the R counter to the output of the VCO determines a lot of the critical performance characteristics of the PLL. The closed loop bandwidth of this system is referred to as the loop bandwidth (Fc), which is an important parameter for both the design of the loop filter and the performance of the PLL. Note that Fc will be used to refer to the loop bandwidth in Hz and ωc will be used to refer to the loop bandwidth in radians. Another parameter, phase margin ( φ), refers to 180 degrees minus the phase of the open loop phase transfer function from the output of the R counter to the output of the VCO. The phase margin is evaluated at the frequency that is equal to the loop bandwidth. This parameter has less of an impact on performance than the loop bandwidth, but still does have a significant impact and is a measure of the stability of the system. The PLL as a Frequency Synthesizer The PLL has been around for many decades. Some of its earlier applications included keeping power generators in phase and synchronizing to the sync pulse in a TV Set. Still other applications include recovering a clock from asynchronous data and demodulating an FM modulated signal. However, the focus of this book is the use of a PLL as a frequency synthesizer. In this type of application, the PLL is used to generate a set of discrete frequencies. A good example of this is FM radio. In FM radio, the valid stations range from 88 to 108 MHz, and are spaced MHz apart. The PLL generates a frequency that is MHz less than the desired channel, since the received signal is mixed with the PLL signal to always generate an IF (Intermediate Frequency) of MHz. Therefore, the PLL generates frequencies ranging from MHz to MHz. The channel spacing would be equal to the parison frequency, which would is 100 fixed crystal frequency of 10 MHz can be divided by an R value of 100 to yield a parison frequency of 100 kHz. Then the N value ranging from 773 to 973 is programmed into the PLL. If the user is listening to a。tsverteilung In Spektrallinien. II.”,. 81 (1933) 428. [13]王德凡、蘭海峰、劉佑華 .MOTOROLA大規(guī)模集成電路鎖相環(huán)頻率合成器 器件 [J].， . 陜西理工學(xué)院畢業(yè)論文（設(shè)計） 第 24 頁 共 31 頁 附錄 A 英文文獻原文 PLL Overview 出處： PLL Performance, Simulation, and Design 3rd Edition（ 110） Dean Banerjee Basic PLL Operation and Terminology This section describes basic PLL (PhaseLocked Loop) operation and introduces terminology that will be used throughout this book. The PLL starts with a stable crystal reference frequency, XTAL, which is divided down to a lower frequency by the R counter. This divided frequency is called the parison frequency (Fp) and is one of the inputs to the phase detector. The phasefrequency detector outputs a current that has an average DC value proportional to the phase error between the parison frequency and the output frequency, after it is divided by the N divider. The constant of proportionality is called K φ. This constant turns out to be the magnitude of the current that the charge pump can source or sink. Although it is technically correct to divide this term by 2π, it is unnecessary since it is canceled out by another factor of 2π which es from the VCO gain for all of the equations in this book. So technically, the units of K φ are expressed in mA/(2π radians).If one takes this average DC current value from the phase detector and multiplies it by the impedance of the loop filter, Z(s), then the input voltage to the VCO (Voltage Controlled Oscillator) can be found. The VCO is a voltage to frequency converter and has a proportionality constant of Kvco. The loop filter is a low pass filter, often implemented with discrete ponents. The loop filter is application specific, and much of this book is devoted to the loop filter. This tuning voltage adjusts the output phase of the VCO, such that its phase, when divided by N, is equal to the phase of the parison frequency. Since phase is the integral of frequency, this implies that the frequencies will also be matched, and the output frequency will be given by OUTF N XTALR??（ ） 陜西理工學(xué)院畢業(yè)論文（設(shè)計） 第 25 頁 共 31 頁 This applies only when the PLL is in the locked state。Sons， 1981. [11]Holmes,.,Coherent Spread Spectrum Systems, John Wileyamp。 同時還要感謝答辯組 老師 在百忙之中抽時間 完 成 了 全面的 評定 工作 。 此 次設(shè)計中難免 有不足之處，但是通過此次設(shè)計，提高了我分析問題和解決問題的能力，使我對所學(xué)知識有了更好的認識，并能應(yīng)用與實踐中去；而 且我對 時頻信號有了一定的了解， 然而 以時頻信號作為基準(zhǔn)信號，這一部分由于對設(shè)備的精度 和穩(wěn)定性 要求高，目前正在 研究中。 電感的制作，繞出來的電量小，在選擇漆包線時不要選強度太硬的，繞的時候最好用中性筆芯來繞，繞的時候一圈和一圈盡量挨緊，如果有條件的話，最好用高頻 Q表測量電感的值； 去藕電容的設(shè)計，為了減少外部的干 擾，一般在芯片的電源和地之間接一大一小兩個電容，稱為 去藕電容，去藕電容因該盡可能的靠近芯片； 分頻器是否正常工作，只有當(dāng)輸入的頻率，和頻率的幅度達到一定值時，分頻器才能正常工作，如果是幅度不夠大，可以通過調(diào)節(jié) MC1648 的 5 腳對地接的電容來改變增益； 壓控振蕩器不起振，檢測 MC1648 的電源是否加好，再檢查繞的線圈是否插好，兩個端上的漆是否刮干凈； 頻率的后兩位不穩(wěn)定，一直 在閃，說明濾波器沒有做好，可以在壓控振蕩器的電壓輸入端加一個上拉電阻； 6 、 在壓控振蕩器周圍盡量減少不必要的布線，避免跳線，電 容的引腳盡可能的短 。 測到的波形如下所示： v? R? HV HV LV LV Vf = Rf = 陜西理工學(xué)院畢業(yè)論文（設(shè)計） 第 21 頁 共 31 頁 結(jié)束語 本課題是一個