【正文】 C, VCC = + to +, CL = 1 TTL Gate and100 pF (unless otherwise noted).Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer toData Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A hightolow transition of SDA with SCL high is a start conditionwhich must precede any other mand (refer to Start and Stop Definition timing diagram).STOP CONDITION: A lowtohigh transition of SDA with SCL high is a stop condition which terminates all munications. After a read sequence, the stop mand will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8bit words. Any device on the system bus receiving data (when municating with the EEPROM) must pull the SDA bus low to acknowledge that it has successfully received each word. This must happen during the ninth clock cycle after each word received and after all other system devices have freed the SDA bus. The EEPROM will likewise acknowledge by pulling SDA low after receiving each address or data word (refer to Acknowledge Response from Receiver timing diagram).STANDBY MODE: The AT24C01 features a low power standby mode which is enabled: (a) upon powerup and (b) after the receipt of the STOP bit and the pletion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps:(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then(c) create a start condition as SDA is high. Write Operations BYTE WRITE: Following a start condition, a write operation requires a 7bit data word address and a low write bit. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8bit data word. Following receipt of the 8bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internallytimed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle , tWR, and the EEPROM will not respond until the write is plete (refer to Figure 1).PAGE WRITE: The AT24C01 is capable of a 4byte page write.A page write is initiated the same as a byte write but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to three more data words. The EEPROM will respond with a zero after each data word microcontroller must terminate the page write sequence with a stop condition (refer to Figure 2). The data word address lower 2 bits are internally incremented following the receipt of each data word. The higher five data word address bits are not incremented, retainingthe memory pag。C,VCC = + to + (unless otherwise noted). AC Characteristics:Applicable over remended operating range from TA =40176。C, VCC = + to +, TAC =0176。C, f = MHz, VCC = +.DC Characteristics:Applicable over remended operating range from: TAI=40176。愿大家在今后的人生道路中一切順利。 同時也要感謝我所在公司的項目經(jīng)理，他讓我知道了，在工作中要注意的問題，在畢業(yè)設(shè)計中也感謝他給與我的支持和幫助。這些在人生中將教導(dǎo)我們一生。在工作中深深的感到平時學(xué)習(xí)的東西的重要。首先我很感謝齊老師給我的幫助，設(shè)計中我遇到了很多問題，每次通過網(wǎng)絡(luò)向齊老師請教，齊老師都很細心的給我講解。本文討論了用軟件模擬并行總線控制LCM的方法, 電路簡單、使用方便具有很好的通用性。由于該方法可移植性很強,因此稍做修改就可應(yīng)用于其他實際工程項目,方便設(shè)計開發(fā)。本文所述的基于C51匯編語言的單片機控制LCD驅(qū)動器的方法是在實際工作中總結(jié)出的,僅從應(yīng)用角度介紹了控制的原理,沒有詳細介紹工作模式、命令格式及圖形算法。 結(jié)　論實踐證明本系統(tǒng)硬件電路簡單, 程序簡潔, 通用性強, 達到了設(shè)計的目的, 為各種人機交互界面的設(shè)計, 提供了一種有效的方法。能達到我們預(yù)期結(jié)果，則系統(tǒng)工作正常，方案正確。以上為我們在做系統(tǒng)測試需要讓LCD顯示的內(nèi)容及格式。在顯示的時候我們需要簡單的排版，將“三角波”漢字放在第一行，頻率放在第二行，頻率數(shù)據(jù)放在漢字后面，且漢字與數(shù)據(jù)有“：”隔開。 測試方案：用VHDL編寫一個信號發(fā)生器程序，讓LCD顯示信號的波形類型和頻率及幅度。 整體系統(tǒng)測試 本設(shè)計的目的基于FPGA和單片機通信及單片機驅(qū)動LCD顯示。經(jīng)測試p0口數(shù)據(jù)隨p1，p2口數(shù)據(jù)輸入發(fā)生相應(yīng)的變化且為我們預(yù)想的結(jié)果，則單片機驅(qū)動程序正確。通過調(diào)試工具，在軟件中對代碼進行測試。167。圖51 FPGA模塊仿真圖（a）仿真圖各個信號作用在前段以作介紹，圖中wradd從0開始遞增，通過wrclk將data1數(shù)據(jù)寫入存儲器模塊內(nèi)，此過程為存儲器寫。Txd每來一個高電平表示讀數(shù)成功傳給單片機數(shù)據(jù)更新可以進行后面的操作。第5章 系統(tǒng)測試與結(jié)果仿真167。 您可以使用 Quartus II Block Editor、Text Editor、MegaWizard PlugInManager （Tools 菜單）和 EDA 設(shè)計輸入工具建立包括 Altera 宏功能模塊、參數(shù)化模塊庫 (LPM) 函數(shù)和知識產(chǎn)權(quán) (IP) 函數(shù)在內(nèi)的設(shè)計。Quartus軟件可以將設(shè)計、綜合、布局和布線以及系統(tǒng)的驗證全部都整合到一個無縫的環(huán)境之中，其中還包括和第三方EDA工具的接口。圖22說明了Quartus軟件的開發(fā)流程。Quartus集成環(huán)境包括以下內(nèi)容：系統(tǒng)級設(shè)計、嵌入式軟件開發(fā)、可編程邏輯器件(PLD)設(shè)計、綜合、布局布線、驗證和仿真。167。uVision2調(diào)試器為你實際目標(biāo)板上測試你的程序提供了幾種方法： 安裝MON51目標(biāo)監(jiān)控器到你的目標(biāo)系統(tǒng)并且通過MONITOR51接口下載你的程序。uVision2源代碼級調(diào)試器是一個理想的快速，可靠的程序調(diào)試器。 與開發(fā)工具手冊和器件數(shù)據(jù)手冊和用戶指南有直接的鏈接。 真正的源代碼級的對CPU和外圍器件的調(diào)試器。 集成的MAKE工具可以匯編，編譯和連接你的嵌入式應(yīng)用。 器件庫用來配置開發(fā)工具設(shè)置。uVision2通過以下特性加速你的嵌入式系統(tǒng)的開發(fā)過程。 系統(tǒng)調(diào)試軟件Keil uVision2uVision2IDE是一個基于的開發(fā)平臺，包括一個高效的編輯器一個項目管理器和一個MAKE工具。下圖軟件設(shè)置（a）為字母字符數(shù)字取模軟件設(shè)置，（b）為漢字取模設(shè)置方式。626301。167。 LCD 讀控制狀態(tài)標(biāo)志 RDY： CLR DI ；讀狀態(tài)標(biāo)志 CLR RW SETB E MOV A，P0 ；讀LCD狀態(tài) CLR E JB ,RDY ；檢測BUSY位 RETWI: SETB CS1 ；寫控制指令 SETB CS2 LCALL RDY ；檢測BUSY位 CLR DI CLR RW MOV P0,20H ；向LCD寫數(shù)據(jù) SETB E ；使能信號E=1 CLR E ；使能信號E=0 CLR CS1 CLR CS2 RETWD1: SETB CS1 ；寫顯示數(shù)據(jù)（左） LCALL RDY ；檢測BUSY位 SETB DI CLR RW MOV P0,20H 。 ● 讀顯示數(shù)據(jù)（Read Display Data） RSR/WDB7DB7DB5DB4DB3DB2DB1DB0顯 示 數(shù) 據(jù) 根據(jù)GDM12864A的軟件顯示特性?！?寫顯示數(shù)據(jù)（Write Display Data）RSR/WDB7DB7DB5DB4DB3DB2DB1DB0顯 示 數(shù) 據(jù) 該操作將8位數(shù)據(jù)寫入先前已確定的顯示存儲器的單元內(nèi)。Y地址計數(shù)器具有自動加一功能，在每一次讀／寫數(shù)據(jù)后它將自動加一，所以在連續(xù)進行讀／寫數(shù)據(jù)時，Y地址計數(shù)器不必每次都設(shè)置一次。該指令規(guī)定了以后的讀／寫操作將在哪一個頁面上進行?！?頁面地址設(shè)置[Set Page（X address）]RSR/WDB7DB7DB5DB4DB3DB2DB1DB00010111Page(0~7) 該指令設(shè)置了頁面地址—X地址寄存器的內(nèi)容。HD612O2U有64行顯示的管理能力，該指令中 L5～LO為顯示起始行的地址，取值在O～3FH（1～64行）范圍內(nèi)，它規(guī)定了顯示屏上最頂一行所對應(yīng)的顯示存儲器的行地址。當(dāng) D=0為關(guān)顯示設(shè)置，顯示數(shù)據(jù)鎖存器被置零，顯示屏呈不顯示狀態(tài)，但顯示存儲器并沒有被破壞，在狀態(tài)字中 ON／OFF＝1。當(dāng)D=1為開顯示設(shè)置，顯示數(shù)據(jù)鎖存器正常工作，顯示屏上呈現(xiàn)所需的顯示效果。● 顯示開關(guān)設(shè)置（Display on／off） RSR/WDB7DB7DB5DB4