【正文】 隨著信息處理技術的飛速發(fā)展，計算機技術和數字信號處理技術數字信號處理技術逐漸發(fā)展成為它在電子信息、通信、軟件無線電、自動控制、儀表技術、信息家電等高科技領域得到了越來越廣泛的應用。作為數字化最重要的技術之一，DSP無論在其應用的深度還是廣度，正在以汀所未有的速度向前發(fā)展。沈陽航空工業(yè)學院學報，[4]孫克梅，劉洋. 隨著數字技術的發(fā)展，用數字技術實現濾波器的功能越來越受到人們的注意和廣泛的應用。因此，數字濾波器本身既可以是用數字硬件裝配成的一臺完成給定運算的專用的數字計算機，也可以將所需要的運算編成程序，讓通用計算機來執(zhí)行。用可編程DSP芯片實現數字濾波可通過修改濾波器的參數十分方便的改變?yōu)V波器的特性。 數字濾波器容易實現不同的幅度和相位頻率特性指標，克服了與模擬濾波器器件性能相關的電壓漂移、溫度漂移和噪聲問題。 近年來，DSP技術在我國也得到了迅速的發(fā)展，不論是在科學技術研究，還是在產品的開發(fā)等方面，在數字信號處理中，其應用越來越廣泛，并取得了豐碩的成果。數字信號處理由于運算速度快，具有可編程特性和接口靈活的特點，使得它在許多電子產品的研制、開發(fā)和應用中，發(fā)揮著重要的作用。具有高度專業(yè)化的指令系統(tǒng)，包括單指令重復和塊指令重復操作，塊存儲器傳輸指令，32位長操作數指令，同時讀入2或3個操作數的指令，能并行存儲和并行加載的算術指令，條件存儲指令和從中斷快速返回[2] [M].北京：電子工業(yè)出版社，2007.因此編程時不能隨便向這個區(qū)域存儲數據，除非根據需要來改變相應寄存器的值，否則會導致程序運行結果錯誤。數據存儲空間還有一塊特殊的區(qū)域，00H~08H。DRAM一般由若干塊構成，由于每塊DARAM在一個機器周期內可以被訪問2次，中央處理單元和片內外設在一個周期內可以同時對其進行一次讀和一次寫操作。器片內存儲器的種類只要有以下幾種:雙訪問RAM(DARAM)，單訪問RAM(SRAM)和ROM。Ineterface)接口，兩個多通道緩沖串行口McBSP(Multichannel 摘要： DSP5402的片上外圍電路包括:通用I/O引腳(XF和BIO)，定時器，時鐘發(fā)生器，一個與外部處理器通信的8位的HPI(Host數字濾波器的DSP實現[J]。 FIR濾波器的級聯型結構。這種結構的每一節(jié)控制一對零點，因而再需要控制傳輸零點時，可以采用它。若N為偶數，則N—1為奇數，故系數B2K中有一個為零，這是因為，這時有奇數個根，其中復數根成共軛對必為偶數，必然有奇數個實根。將轉置定理用于轉置直接型結構。FPGA有著規(guī)則的內部邏輯塊陣列和豐富的連線資源，特別適合用于細粒度和高并行度結構的FIR濾波器的實現，相對于串行運算主導的通用DSP芯片來說，并行性和可擴展性都更好。而且，就是同一公司的不同系統(tǒng)的DSP芯片，其編程指令也會有所不同，開發(fā)周期較長。DSP芯片有專用的數字信號處理函數可調用，或者根據芯片指令集的結構自行設計代碼實現FIR的功能；由于FIR設計時其系數計算及其量化比較復雜，因此一般都采用MATLAB軟件作為輔助設計，計算出FIR的系數；然后進行代碼設計實現。雖然可采用多片擴展來滿足要求，但會增加體積和功耗，因而在實際應用中受到限制。FPGA有著規(guī)整的內部邏輯陣列和豐富的連線資源，特別適合于數字信號處理任務，相對于串行運算為主導的通用DSP芯片來說，其并行性和可擴展性更好，利用FPGA乘累加的快速算法，可以設計出高速的FIR數字濾波器。關鍵詞:FIR 濾波器 數字濾波器是數字信號處理中最重要的部分之一，用有限精度算法的離散時間線性非時變系統(tǒng)，其輸入是一組(由模擬信號采樣和量化)數字量，數字濾波器沒有漂移，能夠處理低頻信號，頻率響應可以非常接近于理想的特性，并且可以達到精度高，容易集成等，這些優(yōu)勢決定了數字濾波器的應用越來越廣泛。 Then for code design implementation. Realization of FIR filter is relatively simple， but because of Program order execution， the speed is restricted. And different system of DSP chip is the same pany， its programming instructions will also vary， development cycle is long.Programmable Another is the use of programmable logic device， FPGA/CPLD. FPGA has the rules of the internal logic of array and rich resources of attachment， especially suitable for fine grain and high parallelism of the structure of the FIR filter implementation， relative to the serial operation of general purpose DSP chip， parallelism and scalability are better. The characteristics of Finite length unit impulse response (FIR) filter has the following features: (1) the system of unit impulse response h (n) in a finite number of n value is zero (2) the system function H (z) in the | z | 0 convergence， the poles all at z = 0 (causal system) (3) the structure of the main is a recursive structure， there is no output to the input feedback， but some of the structures (such as frequency sampling structure) also contains a recursive part of feedback. A FIR filter unit impulse response h (n) for a sequence of n point 0 n n 1 or less， or less filter system function H (z) = ∑ H (n) * z ^ n That is， it has (N 1) order pole at z = 0， has a limited (N 1) a zero in any position of the z plane.The basic structure FIR filter has the following basic structure: Crosssectional shape () of the expression system of difference equations Y (n) = ∑ h (m) x (n， m) () Obviously， this is the convolution of the linear shift invariant system and formula， also delay chain lateral structure of x (n)， as shown in figure 4 to 11， referred to as the transverse structure or convolution model structure， also known as direct type structure. Used in figure 4 to 11 will be transposed theorem， available figure 412 transpose structure directly. Figure cross sectional type structure of FIR filter Cascade type H (z) is resolved into multiplication of coefficient of secondorder factors () Said one [N / 2] take the integer part of N / 2. If N is even， it is an odd number of N 1， so the coefficient has a zero in the B2K， this is because， at this time there are an odd number of root， the conjugate plex roots into the will is even， there must be an odd number of real root. Figure 713 draw N is odd， cascade structure of FIR filter， each a secondorder factor in figure 411 horizontal structure of each section to control a pair of zero， and then the need to control transmission zeros， it can be used. But this structure need coefficient B2k (I = 0， k = 1， 2，...， N / 2) than convolution model coefficient of h (N)， and the required number of multiplication also more than convolution model.譯文數字濾波器科斯特奧特摘要：FIR(Finite Impulse Response)濾波器：有限長單位沖激響應濾波器，是數字信號處理系統(tǒng)中最基本的元件，它可以在保證任意幅頻特性的同時具有嚴格的線性相頻特性，同時其單位抽樣響應是有限長的，因而濾波器是穩(wěn)定的系統(tǒng)。s output must be D/A converter module. FPGA has a wellorganized internal logic array and rich connection resources， particularly suitable for digital signal processing tasks， relative to the serial port operation as the leading general DSP chip， its better parallelism and scalability， using fast algorithm of FPGA by accumulation， can design a high speed FIR digital filter.Hardware category: The hardware realization of FIR filter has the following several ways:Integrated Circuit: Is a kind of digital filter monly used in monolithic integrated circuit， the circuit is simple to use， but because of the word length and the specifications of the order number is less， not easy to fully meet the actual needs. Although multiple extension can be used to meet the requirements， but will increase the volume and power consumption， thus limited in practical application.DSP Chip Another is the use of DSP chip. DSP chip is a dedicated digital signal processing function can call， or according to the structure of the chip instruction set design code can realize the function of FIR。 In order to make the signal processing can not occur distortion， the signal must satisfy is the Nyquist sampling speed of a specific reason， generally take signal frequency limit of 45 times as the sampling frequency。[10]張雄偉，陳亮，(3版)[M].北京:電子工業(yè)出版社，沈陽航空工業(yè)學院學報，[9]孫克梅，劉洋.DSP應用程序設計與開發(fā)[M].北京