freepeople性欧美熟妇, 色戒完整版无删减158分钟hd, 无码精品国产vα在线观看DVD, 丰满少妇伦精品无码专区在线观看,艾栗栗与纹身男宾馆3p50分钟,国产AV片在线观看,黑人与美女高潮,18岁女RAPPERDISSSUBS,国产手机在机看影片

正文內(nèi)容

模擬集成電路的設(shè)計(jì)流程(參考版)

2025-01-11 15:09本頁面
  

【正文】 digital stop views to match the stop views in your hierarchy editor (as below) 2022/2/4 共 88頁 79 Check Partition Results 設(shè)定顯示的顏色及項(xiàng)目 顯示所有模塊劃分的結(jié)果 顯示模擬電路模塊 顯示數(shù)字電路模塊 顯示混合信號(hào)電路模塊 顯示無法規(guī)類的電路模塊 清除所有顯示內(nèi)容 2022/2/4 共 88頁 80 Partition Requirement ? The design must contain at least one analog ponent. ? The design must contain at least one digital ponent. ? There must be with at least one interface . ? Analog stimuli defined in the analog stimuli file cannot be used to drive digital . ? Digital stimuli defined in the digital stimuli file can not be used to drive analog . ? Any interface must be identified before listing. 2022/2/4 共 88頁 81 Setup the analog/digital interface Select: MixedSignal Interface Elements Instance this tool is used to configure how the digital block reads analog inputs and how digital outputs are seen by analog cells (effective A/D and D/A). 2022/2/4 共 88頁 82 Setup the analog/digital interface MOS_a2d: A2D_V0 低電平 A2D_V1 高電平 A2D_TX: voltage between V0 and V1 after TX will yield a logic X MOS_d2a: Model Parameters D2A_VL : input low voltage D2A_VH : input high voltage D2A_TR : rise time for low to high D2A_TF : fall time for high to low 2022/2/4 共 88頁 83 Setup Menu in Analog Environment With Setup window to define simulation initialization setup ?Choose the simulator ?Define device model library ?Define temperature …… 2022/2/4 共 88頁 84 Choosing Simulator/Directory/Host 選擇 SpectreVerilog 2022/2/4 共 88頁 85 Choose Analysis Type Invoke the analysis setting window For MixedSignal simulation, only tran is meaningful Set the simulation time Check this box to enable this simulation 2022/2/4 共 88頁 86 Submit the Simulation Execute the simulation job with Run, or create the list with Netlist start simulation 2022/2/4 共 88頁 87 Results 其中 clk:數(shù)字模擬輸入 DIGITAL_OUT:數(shù)字輸出 ANALOG_OUT :模擬輸出 2022/2/4 共 88頁 88 THANK YOU! 。 ? 同時(shí)包含模擬和數(shù)字兩個(gè)仿真核 處理速度快,能處理的電路規(guī)模極大,但需要解決模擬仿真核和數(shù)字仿真 核之間的通信問題;另外,由于數(shù)字邏輯仿真器和模擬仿真器的輸入、輸 出數(shù)據(jù)是不一樣的,還必須在模擬仿真核和數(shù)字仿真核之間實(shí)現(xiàn)模擬信號(hào) 和數(shù)字信號(hào)的相互轉(zhuǎn)換。 優(yōu)點(diǎn): 模擬結(jié)果精確、能處理的電路規(guī)模比較大,模擬速度也有顯著提高。版本是 2022/2/4 共 88頁 59 修改 *.sp文件 在進(jìn)行 Hspice仿真之前,還要對(duì)剛剛生成的 *.sp文件進(jìn)行修改,如圖所示,添加 hspice的庫文件和仿真精度( tt ff ss fs sf) 注意:庫文件的具體路徑要寫對(duì),而且要是 Hspice的庫 POST 必須加上 2022/2/4 共 88頁 60 用 Hspice進(jìn)行仿真 仿真 查看錯(cuò)誤信息 波形查看器 2022/2/4 共 88頁 61 AvanWaves波形觀察器 2022/2/4 共 88頁 62 AvanWaves波形觀察器 2022/2/4 共 88頁 63 Spectre –Verilog 數(shù)?;旌戏抡? ? Push the limit of system performance Reduce parasitic Reduce I/O driving loads Exploit design space between blocks ? Push the limit of power dissipation Reduce parasitic loads Reduce I/O driving currents ? Reduce the system size Why Mixed
點(diǎn)擊復(fù)制文檔內(nèi)容
環(huán)評(píng)公示相關(guān)推薦
文庫吧 www.dybbs8.com
備案圖鄂ICP備17016276號(hào)-1