【正文】 C regardless of the voltage input on the VCC pin. MOT (Mode Select) – The MOT pin offers the flexibility to choose between two bus types. When connected to VCC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel bus timing is selected. The pin has an internal pull down resistance of approximately 20 k?. SQW (Square Wave Output) – The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the Real Time Clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 1. The SQW signal c an be 蘇州大學(xué)本科生畢業(yè)論文（設(shè)計(jì)） 25 turned on and off using the SQWE bit in Register B. The SQW signal is not available when VCC is less than volts, typically. PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 1 SELECT BITS REGISTER A tPI PERIODIC INTERRUPT RATE SQW OUTPUT FREQUENCY RS3 RS2 RS1 RS0 0 0 0 0 None None 0 0 0 1 ms 256 Hz 0 0 1 0 ms 128 Hz 0 0 1 1 ms kHz 0 1 0 0 ms kHz 0 1 0 1 ms kHz 0 1 1 0 ms kHz 0 1 1 1 ms 512 Hz 0 0 0 0 ms 256 Hz 0 0 0 1 ms 128 Hz 0 0 1 0 ms 64 Hz 0 0 1 1 ms 32 Hz 0 1 0 0 ms 16 Hz 0 1 0 1 125 ms 8 Hz 0 1 1 0 250 ms 4 Hz 0 1 1 1 500 ms 2 Hz 蘇州大學(xué)本科生畢業(yè)論文（設(shè)計(jì)） 26 AD0–AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins because address information and data information timeshare the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS12887 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS/ ALE, at which time the DS12887 latches the address from AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR pulses. In a read cycle the DS12887 outputs 8 bits of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of Motorola timing or as RD transitions high in the case of Intel timing. AS (Address Strobe Input) – A positivegoing address strobe pulse serves to demultiplex the bus. The falling edge of AS/ALE causes the address to be latched within the DS12887. The next rising edge that occurs on the AS bus will clear the address regardless of whether CS is asserted. Access mands should be sent in pairs. DS (Data Strobe or Read Input) – The DS/RD pin has two modes of operation depending on the level of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is selected. In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data Strobe. During read cycles, DS signifies the time that the DS12887 is to drive the bidirectional bus. In write cycles the trailing edge of DS causes the DS12887 to latch the written data. When the MOT pin is connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read (RD ).RD identifies the time period when the DS12887 drives the bus with read data. The RD signal is the same definition as the Output Enable (OE ) signal on a typical memory. R/W (Read/Write Input) – The R/ W pin also has two modes of operation. When the MOT pin is connected to VCC for Motorola timing, R/ W is at a level which indicates whether the current cycle is a read or write. A read cycle is indicated with 蘇州大學(xué)本科生畢業(yè)論文（設(shè)計(jì)） 27 a high level on R/ W while DS is high. A write cycle is indicated when R/ W is low during DS. When the MOT pin is connected to GND for Intel timing, the R/ W signal is an active low signal called WR. In this mode the R/W pin has the same meaning as the Write Enable signal ( WE ) on generic RAMs. CS (Chip Select Input) – The Chip Select signal must be asserted low for a bus cycle in the DS12887 to be accessed. CS must be kept in the active state during DS and AS for Motorola timing and during RD and WR for Intel timing. Bus cycles which take place without asserting CS will latch addresses but no access will occur. When VCC is below volts, the DS12887 internally inhibits access cycles by internally disabling the CS input. This action protects both the real time clock data and RAM data during power outages. IRQ (Interrupt Request Output) – The IRQ pin is an active low output of the DS12887 that can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt–enable bit is set. To clear the IRQ pin the processor program normally reads the C register. The RESET pin also clears pending interrupts. When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an external pull up resistor. RESET (Reset Input) – The RESET pin has no effect on the clock, calendar, or RAM. On power–up the RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of time that RESET is held low is dependent on the application. However, if RESET is used on power–up, the time RESET is low should exceed 200 ms to make sure that the internal timer that controls the DS12887 on powerup has timed out. When RESET is low and VCC is above volts, the following occurs: A. Periodic Interrupt Enable (PEI) bit is cleared to 0. B. Alarm Interrupt Enable (AIE) bit is cleared to 0. C. Update Ended Interrupt Flag (UF) bit is cleared to 0. 蘇州大學(xué)本科生畢業(yè)論文（設(shè)計(jì)） 28 D. Interrupt Request Status Flag (IRQF) bit is cleared to