基于systemview的2dpsk信號(hào)傳輸仿真-wenkub.com
2025-06-19 17:14 本頁面
【正文】 圖符8控制SNR，每次循環(huán)后將信噪比遞增1Db,圖符23對(duì)輸入端采樣序列延時(shí)，使BER計(jì)數(shù)器的兩個(gè)輸入端位同步。為了分析碼反變換器對(duì)誤碼的影響，我們做出一組圖形來加以說明。我們這里討論相干解調(diào)碼反變換器的方式，分析模型如圖（a）所示。 實(shí)驗(yàn)內(nèi)容：以2DPSK作為系統(tǒng)輸入信號(hào)，碼速率Rb＝10kbit/s。 圖26 輸出PN序列的基帶譜通過比較相干解調(diào)法和非相干解調(diào)法可以看出，相干解調(diào)法需要提取相干載波，還要進(jìn)行碼反變換，即將相對(duì)碼變換為絕對(duì)碼；而非相干解調(diào)法不需要提取相干載波，也不需要進(jìn)行碼反變換。圖19 眼圖圖19的眼圖是沒有加噪聲情況下的仿真結(jié)果，眼圖張開度較大，掃跡清晰。表3：相干解調(diào)法圖符參數(shù)設(shè)置表編號(hào)庫/名稱參 數(shù)9Butterworth Bandpass IIR3 Poles Low Fc = 20e+3 HzHi Fc = 60e+3 Hz Quant Bits = NoneInit Cndtn = Transient DSP Mode DisabledFPGA Aware = True RTDA Aware = Full10Multiplier:Non ParametricInputs from 11 9 Outputs to 12 2311Comm: CostasVCO Freq = 40e+3 Hz VCO Phase = 0 deg Mod Gain = 1 Hz/vLoop Fltr = 1 + 1/s + 1/s^2 Output 0 = Baseband InPhase Output 1 = Baseband Quadrature Output 2 = VCO InPhase Output 3 = VCO Quadrature t10 t25 RTDA Aware = Full12Operator: Linear SysBessel Lowpass IIR3 Poles Fc = 16e+3 Hz Quant Bits = None Init Cndtn = TransientDSP Mode Disabled FPGA Aware = True RTDA Aware = Full13Operator: SamplerInterpolating Rate = 20e+3 Hz Aperture = 0 sec Aperture Jitter = 0 sec14Operator: HoldLast Value ，Gain = 1 ，Out Rate = 400e+3 HzFalse Output = 1 v，Rise Time = 0 sec，F(xiàn)all Time = 0 sec15Logic: BufferGate Delay = 0 sec Threshold = 0 v True Output = 1 v False Output = 1 v Rise Time = 0 sec Fall Time = 0 sec16Logic: XORGate Delay = 0 sec Threshold = 0 v True Output = 1 v False Output = 1 v Rise Time = 0 sec Fall Time = 0 sec17Operator: DelayNonInterpolating Delay = secOutput 0 = Delay t16 Output 1 = Delay dT 調(diào)制信號(hào)為PN序列，碼速率Rb＝10kbit/s；正弦載波的頻率為20k Hz。圖1 4 差分譯碼器 系統(tǒng)組成、圖符塊參數(shù)設(shè)置及仿真結(jié)果：相干解調(diào)法：相干解
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