【正文】 這主要是因為本文的目的是要提出一個頻率測量的替代原理。換句話說，循環(huán)有能力按照輸入信號頻率的變化而改變。另一方面，由于 DDS 的固有高頻率的特點，該方法的精度非常高。在數(shù)字示波器的幫助下，測量采用較低速度跟蹤檢查。這次調(diào)整階段一部分實施在 PLD 一部分在微控制器。該 12 位輸出的 LUT送入到由模擬設(shè)備 AD9713B 發(fā)出的 D / A 轉(zhuǎn)換器中。 接下來，一個更高的頻率原型制造出來了，在此進行更詳細的描述。這里的坡度為 ? k ? fin。下跟蹤的 U / D 命令（輸入）到計數(shù)器上，而跟蹤是一個假設(shè)的 “ 調(diào)頻 ” 波形被不同的規(guī)定。較低的形跡顯示一個 比較典型的頻率輸出。當 DDS輸出（ fDDS）已接近鰭，由于滯后性，沒有特定的頻率合成。在最初的DDS 頻率低時，合成頻率將會逐步增加，達到未知之一。這種情況被控制，也將在后面解釋。這實際上是一個可以接受的和預(yù)期的條件，因為（在電壓比較器）的平等是不可能存在的跡象。 遲滯取決于最初的 DDS 輸出時序關(guān)系和未知頻率。不幸的是并非如此。 RS 觸發(fā)器的邏輯 “1” 在向上 /向下計數(shù)器的 U / D 的控制輸出中起作用，強制 DDS 升高輸出頻率。它主要包括兩個二進制計數(shù)器，共計兩個和一個 RS 觸發(fā)器 。 或者，也可以進行數(shù)字記錄，也可以由計算機閱讀。根據(jù)比較器輸出的頻率，在每一個近似值中頻率被分成兩個并且增加或減少到 DDS 的 FSW 中。中北大學(xué) 2020 屆英文文獻及中文翻譯 第 3 頁 共 6 頁 這一階段也可用于測量提取 ，以顯示正確的讀數(shù) 。 時鐘頻率下降的影響是其最大輸出頻率，限制計數(shù)器的最大計數(shù)隨之降低。在砷化鎵產(chǎn)品來看，我們可以看到，最近的 DDS 設(shè)計可以在高達 400 兆赫的時鐘頻率范圍運作。 產(chǎn)生我們目前的設(shè)計的想法來自 DDS 的頻率分辨率極高的設(shè)備并且由它的封閉循環(huán)的形式抗干擾執(zhí)行。這是該系統(tǒng)能生成的最低的頻率，也是它的頻率分辨率。 在凡方波輸出需要的應(yīng)用中，這由一個硬限制器在經(jīng)過過濾器之后得到。一個相位累加器產(chǎn)生連續(xù)的正弦查找表的地址，并生成一個數(shù)字正弦波輸出。產(chǎn)生上述提及的受控的頻率波形是一個直接數(shù)字合成器。上述方法的特點是開環(huán)方法，即數(shù)字計數(shù)器來計數(shù)在預(yù)定 tinle 間隔，之后計算結(jié)果。本文獻的第 [1]部分的某些文件處理了低頻率的測量問題并集中在心臟（心臟）信號的頻率范圍（幾赫茲）或在電源頻率（ 5060 赫茲）。所有額外相關(guān)的階段都被儀器的顯示器顯示出來。從比較兩個信號的輸出，控制邏輯向上 /向下計數(shù)器產(chǎn)生了。s output will toggle, indicating alternatively that the DDS frequency is higher or lower than the unknown. This is actually an acceptable and expected condition, because (as in a voltage parator) an equality indication could not exist. In our case this is not a problem because the circuit is embedded in a closed loop. The loop will act in a manner that after some short time, the hysteresis, the situation will be reversed and so on. The duration of hysteresis is variable. This situation is controlled, as will be explained later. Although an analog implementation of the frequency parator would look more robust to noise we insisted to the digital implementation for three reasons: ease of implementation in VLSI or Programmable Logic Devices (PLDs) with no need of analog ponents, wide frequency range of operation and shorter response time. Interaction between frequency parator and digital synthesizer After the successive approximation of the unknown frequency the Frequency Comparator realizes that the synthesized frequency is higher (lower) than the unknown one and produces a logic 0 (1) at the output which mands the up/down counter to count in the down (up) direction. As previously mentioned, the output of this counter is considered to be the FSW to the DDS stage. In the case when the DDS frequency was initially lower, the synthesized frequency will increase progressively to reach the unknown one. This will not be realized by the frequency parator and the synthesized frequency will keep on increasing for some clock cycles, until the parator detects the correct relation of it39。 If the phase step is equal to one, the accumulator will count by ones, taking 2n clock cycles to address the entire LUT and to generate one cycle of the output sinewave. This is the lowest frequency that the system can generate and is also its frequency resolution. Setting the FSW equal to two, results in the accumulator counting by twos, taking 12n? clock cycles to plete one cycle of the output sinewave. It can easily be shown that for any integer m, where m 12n? , the number of clock cycles taken to generate one cycle of the output sine wave is 2n /m, and the output frequency (fDDS) and the frequency resolution (fres) are given by the following formulas： fDDS=2nm fclk? fres= fclk/2n For n = 32 and having a clock frequency of fclk = 33 MHz, the frequency resolution is mHz. If n is increased to 48, with the same clock frequency, a resolution of 120 nHz is possible. 3 The proposed frequency measurement technique The idea that led to our present design came from the extremely high frequency resolution of the DDS devices and is enforced by the noise immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a closed loop and is forced progressively to produce an output with a frequency equal to the unknown input . A rule of thumb in the DDS systems is that the maximum acceptable synthesized frequency is about 25% of the clock frequency (well below the Nyquist limit). According to this, our prototype that uses a