【正文】 thus, these ponents are also shaded. In such microcontrollers, the CPU may be quite different from those discussed in this chapter. The word lengths may be short (say, four or eight bits),the number of registers small, and the instruction sets limited. Performance, relatively speaking, is poor, but adequate for the task. Most important, the cost of these microcontrollers is very low, making their use cost effective. In the following pages, we consider two puter CPUs, one for a plex instruction set puter (CISC) and the other for a reduced instruction set puter (RISC). After a detailed examination of the designs, we pare the performance of the two CPUs and present a brief overview of some methods used to enhance that performance. Finally, we relate the design ideas discussed to general digital system design. Two CPU designs As mentioned in previous chapters, atypical CPU is usually divided into two parts: the datapath and the control unit. The datapath consists of a function unit, registers, and internal buses that provide pathways for the transfer of information between the registers, the function unit, and other puter ponents. The datapath may or may not be pipelined. The control unit consists of a program counter, an instruction register, and control logic, and may be other hardwired or microprogrammed. If the datapath is pipelined, the control unit may be also be a 12 pipeline. The puter of which the CPU is a part is either a CISC or a RISC, with its own instruction set architecture. The purposes of this chapter is to present two CPU designs that illustrate binations of architectural characteristics of the instruction set, the datapath, and the control unit. The designs will be top down, but with the reuse of prior ponent designs, illustrating the influence of the instruction set architecture on the datapath and control units, and the influence of the datapath on the unit. The material makes extensive use of tables and diagrams. Although we reuse and modify ponent designs from others , background information from these chapters is not repeated here. References, however, are given to earlier sections of the book, where detailed information can be found. The two CPUs presented are for a CISC using a nonpipelined datapath with a microprogrammed control unit and a RICS using a pipelined datapath with a hardwired pipelined control unit. These represent two quite distinct binations of instruction set architecture, datapath, and control unit. The plex instruction set puter The first design we present is for a plex instruction set puter with a nonpipelined datapath and microprogrammed control unit. We begin by describing the instruction set architecture, including the CPU register set, instruction formats, and addressing modes. The CISC nature of the instruction set architecture is demonstrated by its memorytomemory access for data manipulation instructions, eight addressing modes, two instruction format lengths, and instructions that require significant sequences of operations for their execution. We design a datapath for implementing the CISC architecture. The datapath is based on the one initially described in Section 79 and incorporated into a CPU in section 810. modifications are made to the register file, the function unit, and the buses to support the present instruction set architecture. Once the datapath has been specified, a control unit is designed to plete the implementation of the instruction set architecture. The design of the control unit must involve a coordinated definition of both the hardware organization and the microprogram organization. In particular , dividing the microprogram into microroutines, while at the same time designing the sequencer with which they interact, is a key part of the design. Even the instruction fields and opcodes are tied to this coordinated effort. Following the definition of the hardware and microcode organizations, we detail essential parts of the microcode and the microroutines for representative operations. 13 Instruction set architecture Figure 101 shows the CISC register set accessible to the programmer. All registers have 16 bits. The register file has eight registers, R0 though is a special register that always supplies the value zero when it is used as a source and discards the result when it is used as a destination. In additional to the register file, there is a program counter PC and stack pointer SP. The presence of a stack pointer indicates that a memory stack is a part of the architecture . the final register is the processor status register PSR, which contains information only in its rightmost the five bits。我們研究任何形式的風險，像軟件和硬件一頁提出每個解決方案。 控制單元還具有廣泛的跳躍和有條件的分支能力，包括微型子路線的一個層次。在每個執(zhí)行微線路之后，在獲取下一個指令之前該程序進入了中斷。 繼其執(zhí)行，在目的地中，大部分操作去存放結果是必要的。根據(jù)操作碼（ OPCODE）的前三個位，要么一個單一的操作，兩個操作（或者一個操作加一個參數(shù)），要么一個分支地址，這二者選其一。有三條途徑去解除障礙取決于決策框制定的決策。這個分支被圖中的五個二進制決策框代替。指令解碼過程是以使用 MUX M 和測繪光盤為開始 8 的。這個流動顯示在圖 108 中，這個圖表并不是嚴格的 ASM 圖，因為每個矩形框對應的微線路代表了不同的國家而不是一個單一的國家以及對應 的是多計時周期而不是單一的周期。這些線路有跟在第 810 部分中流水線 CPU 階段相似的標簽。SBR 被用來存儲關于 CAR 的下一代地址，同時一個微子線路是在微路線的要求下為了使微程序執(zhí)行轉向下一個微指令。微程序的程序計數(shù)器，控制處理登記 CAR 按順序的到達下一個地址或者平行登錄。其中之一是控制單元登記：指令登記 IR，程序計數(shù)器 PC 和堆棧指針度 SP。當然，一些已經(jīng)做出的決定就不需要 再進行討論了。一個 2 比 1 多路復用器 MUX SO 選擇的結束位來傳遞到執(zhí)行觸發(fā)器。最后，隨著執(zhí)行要的旋轉是作為切換器的兩端的一個輸入而提供執(zhí)行觸發(fā)器的輸出。這個修改涉及到切換邏輯的最終的位。 0被附加到 DST 和 SRC 的這個三位領域的左邊致使它們能狗處理 RO 到 ，是來自包括四個位的的微指令的地址以致所有的 17 個編程都能被達到。在微指令中有 5 位的空間是用來合并目的地和來源地址的 DSA，再增加 5位空間給 B 地址 SB。該指令集架構使用兩個地址，一個 圖 3 是來源操作，一個是像目的地一樣的其他來源。 我們不能進入 8個基于在指令集內(nèi)可用 3 位登記地址的臨時登記冊。接下去的 8個登記， R8R15，是被用來作為微程序的臨時存儲，并從程序員那就被隱藏。 在第 810節(jié)里，注冊 R8是被作為臨時的存儲位置。這些特征明確指出這是一個復雜指令集計算機（ CISC）的架構。例如， LD, ST, IN, 和 OUT 都可以通過使用在內(nèi)存映射結構里的 MOVE 指令來實現(xiàn)。 在進行下一步之前，明確數(shù)據(jù)路徑來支持指令集構架，我們將簡要的說明構架的特征來界定是復雜指令集計算機（ CISC）或是精簡指令集計算機（ RISC）。 帶有 IR(15:14)=11 的指令是分流的。如果 S等于 0，那么來源使用被 MODE 指定的處理模式，且來