【正文】
the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, and can be configured to be the timer/counter 2 external count input () and the timer/counter 2 trigger input (), respectively, Port 1 also receives the loworder address bytes during Flash programming and verification 齊齊哈爾大學畢業(yè)設計 (論文 ) 37 Port 2 Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the STC89C52, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable (PSEN) is the read strobe to external program memory. When the STC89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage (VPP) during Flash programming. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. 齊齊哈爾大學畢業(yè)設計(論文) 38 譯文: STC89C52 數(shù)據(jù)手冊 功能特性描述 STC89C52 是一種低功耗、高性能 CMOS8 位微控制器,具有 8K 在系統(tǒng)可編程 Flash 存儲器。使用高密度非易失性存儲器技術(shù)制造,與工業(yè) 80C51 產(chǎn)品指令和引腳完全兼容。片上 Flash 允許程序存儲器在系統(tǒng)可編程,亦適于常規(guī)編程器。在單芯片上,擁有靈巧的 8 位 CPU 和在系統(tǒng)可編程 Flash,使得 STC89C52 為眾多嵌入式控制應用系統(tǒng)提供高靈活、超有效的解決方案。 STC89C52 具有以下標準功能; 8k 字節(jié) Flash, 256 字節(jié) RAM, 32 位 I/O 口線,看門狗定時器, 2 個數(shù)據(jù)指針,三個 16 位定時器 /計數(shù)器,一個 6 向量 2 級中斷結(jié)構(gòu),全雙工串行口,片內(nèi)晶振及時鐘電路。另外, STC89C52 可降至 0Hz 靜態(tài)邏輯操作,支持 2 種軟件可選擇節(jié)電模式??臻e模式下, CPU停止工作,允 許 RAM、定時器 /計數(shù)器、串口、中斷繼續(xù)工作。掉電保護方式下, RAM 內(nèi)容被保存,振蕩器被凍結(jié),單片機一切工作停止,直到下一個中斷或硬件復位為止 。 VCC : 電源 GND: 地 P0 口: P0口是一個 8位漏極開路的雙向 I/O口。作為輸出口,每位能驅(qū)動 8個 TTL邏輯電平。對 P0端口寫 “1”時,引腳用作高阻抗輸入。當訪問外部程序和數(shù)據(jù)存儲器時, P0口也被作為低 8位地址 /數(shù)據(jù)復用。在這種模式下, P0具有內(nèi)部上拉電阻。在 flash編程時,P0口也用來接收指令字節(jié);在程序校驗時,輸出指令字節(jié)。程序校驗時,需要外部上拉電阻。 P1 口: P1口是一個具有內(nèi)部上拉電阻的 8 位雙向 I/O 口, p1 輸出緩沖器能驅(qū)動 4個 TTL 邏輯電平。對 P1 端口寫 “1”時,內(nèi)部上拉電阻把端口拉高,此時可以作為輸入口使用。作為輸入使用時,被外部拉低的引腳由于內(nèi)部電阻的原因,將輸出電流( IIL)。此外, /計數(shù)器 2的外部計數(shù)輸入( )和時器 /計數(shù)器 2的觸發(fā)輸入( ),在 flash編程和校驗時, P1口接收低 8位地址字節(jié)。 P2 口: P2口是一個具有內(nèi)部上拉電阻的 8 位雙向 I/O 口, P2 輸 出緩沖器能驅(qū)動 4個 TTL 邏輯電平。對 P2 端口寫 “1”時,內(nèi)部上拉電阻把端口拉高,此時可以作為輸入口使用。作為輸入使用時,被外部拉低的引腳由于內(nèi)部電阻的原因,將輸出電流( IIL)。在訪問外部程序存儲器或用 16位地址讀取外部數(shù)據(jù)存儲器(例如執(zhí)行 MOVX @DPTR)時, P2 口送出高八位地址。在這種應用中, P2 口使用很強的內(nèi)部上拉發(fā)送 1。在使用 8位地址(如 MOVX @RI)訪問外部數(shù)據(jù)存儲器時, P2口輸出 P2鎖存器的內(nèi)容。在 flash編程和校驗時, P2口也接收高 8位地址字節(jié)和一些控制信號。 P3 口: P3 口是一個具有內(nèi)部上拉電阻的 8 位雙向 I/O 口, P2 輸出緩沖器能驅(qū)動 4個TTL 邏輯電平。對 P3 端口寫 “1”時,內(nèi)部上拉電阻把端口拉高,此時可以作為輸入口使用。作為輸入使用時,被外部拉低的引腳由于內(nèi)部電阻的原因,將輸出電流( IIL) 。P3口亦作為 STC89C52特殊功能(第二功能)使用,如下表所示。在 flash編程和校驗時,P3口也接收一些控制信號 RST: 復位輸入。晶振工作時, RST腳持續(xù) 2個機器周期高電平將使單片機復位??撮T狗計時完成后, RST 腳輸出 96個晶振周期的高電平。特殊寄存器 AUXR(地址 8EH)上的齊齊哈爾大學畢業(yè)設計 (論文 ) 39 DISRTO位可以使此功能無效。 DISRTO默認狀態(tài)下,復位高電平有效。 ALE/PROG: 地址鎖存控制信號( ALE)是訪問外部程序存儲器時,鎖存低 8 位地址的輸出脈沖。在 flash編程時,此引腳( PROG)也用作編程輸入脈沖。在一般情況下, ALE 以晶振六分之一的固定頻率輸出脈沖,可用來作為外部定時器或時鐘使用。然而,特別強調(diào),在每次訪問外部數(shù)據(jù)存儲器時, ALE脈沖將會跳過。如果需要,通過將地址為 8EH的 SFR的第 0位置 “1”, ALE操作將無效。這一位置 “1”, ALE 僅在執(zhí)行 MOVX 或 MOVC指令時有效。否則, ALE 將被微弱拉高。這個 ALE 使能標志位(地址為 8EH的 SFR的第 0位)的設置對微控制器處于外部執(zhí)行模式下無