【導讀】電子信息工程專業(yè)畢業(yè)論文--基于AT24C01的多功能密。隨著科技的日益發(fā)展電子密碼控制系統(tǒng)已越來越符合人們的要求本文介紹。行了詳細的描述該系統(tǒng)采用AT89C51單片機和AT24C01串行EEPROM通過AT89C51. 模擬I2C總線和AT24C01通訊實現(xiàn)密碼控制的功能。本文從經(jīng)濟實用的角度出發(fā)采用美國Atmel公司的單片機AT89C51作為主控。芯片與數(shù)據(jù)存儲器單元結合外圍的矩陣鍵盤輸入LCD液晶顯示報警開鎖等用C. 語言編寫主控芯片的控制程序與EEPROM讀寫程序相結合設計了一款可以多次更。能控制上鎖開鎖報警修改密碼等多種功能密碼長度可變保密性強靈活性高。經(jīng)實驗證明該密碼控制系統(tǒng)具有設計方法合理簡單易行成本低安全使用等。特點符合車輛辦公室用鎖要求具有推廣價值。關鍵詞密碼控制單片機EEPROM讀寫程序報警。21方案一采用數(shù)字電路控制3. 3主要元器件介紹及I2C總線說明4. AT89C51引腳功能說明5. AT89C51芯片內(nèi)部結構7. 42電路總圖構成15. 更替而使控制的保密性下降。3誤碼輸入保護當輸入密碼多次錯誤時報警系統(tǒng)自動啟動

　　

【正文】 0 NOP NOP iic_clk 1 NOP NOP while iic_sda iic_clk 0 return 1 static void send_ack uchar i 0 iic_sda 1 NOP iic_clk 0 NOP iic_sda 0 NOP iic_clk 1 NOP iic_clk 0 iic_sda 1 void iic_write uchar addruchar dat iic_start iic_write_byte 0xa0 recive_ack iic_write_byte addr recive_ack iic_write_byte dat recive_ack iic_stop static uchar iic_read_byte uchar i uchar dat 0 for i 0i 8i dat 1 iic_clk 0 NOP iic_clk 1 NOP dat iic_sda iic_clk 0 return dat uchar iic_read uchar addr uchar dat iic_start iic_write_byte 0xa0 recive_ack iic_write_byte addr recive_ack iic_start iic_write_byte 0xa1 recive_ack dat iic_read_byte iic_stop return dat void iic_writes uchar addrvoid bufuchar num uchar i uchar pt uchar buf for i 0i numi iic_write addript[i] delay 1000 void iic_reads uchar addrvoid bufuchar num uchar i uchar pt uchar buf for i 0i numi pt[i] iic_read addri delay 1000 附錄三 翻譯 外文資料 1Wire Search Algorithm Abstract Dallas Semiconductors 1Wire devices each have a 64bit unique registration number in readonlymemory ROM That is used to address them individually by a 1Wire master in a 1Wire work If the ROM numbers of the slave devices on the 1Wire work are not known then using a search algorithm can discover them This document explains the search algorithm in detail and provides an example implementation for rapid integration This algorithm is valid for all current and future devices that feature a 1Wire interface Table 1 Bit Unique ROM Registration Number MSB 64Bit Registration ROM Number LSB 8Bit CRC MSB LSB 48Bit Serial Number MSB LSB 8Bit Family Code MSB LSB Search Algorithm The search algorithm is a binary tree search where branches are followed until a device ROM number or leaf is found Subsequent searches then take the other branch paths until all of the leaves present are discovered The search algorithm begins with the devices on the 1Wire being reset using the reset and presence pulse sequence If this is successful then the 1byte search mand is sent The search mand readies the 1Wire devices to begin the search There are two types of search mands The normal search mand 0F0 hex will perform a search with all devices participating The alarm or conditional search mand 0EC hex will perform a search with only the devices that are in some sort of alarm state This reduces the search pool to quickly respond to devices that need attention Following the search mand the actual search begins with all of the participating devices simultaneously sending the first bit least significant in their ROM number also called registration number See Figure 1 As with all 1Wire munication the 1Wire master starts every bit whether it is data to be read or written to the slave devices Due to the characteristics of the 1Wire when all devices respond at the same time the result will be a logical AND of the bits sent After the devices send the first bit of their ROM number the master initiates the next bit and the devices then send the plement of the first bit From these two bits information can be derived about the first bit in the ROM numbers of the participating devices See Table 1 Table 2 Bit Search Information Bit true Bit plement Information Known 0 0 There are both 0s and 1s in the current bit position of the participating ROM numbers This is a discrepancy 0 1 There are only 0s in the bit of the participating ROM numbers 1 0 There are only 1s in the bit of the participating ROM numbers 1 1 No devices participating in search According to the search algorithm the 1Wire master must then send a bit back to the participating devices If the participating device has that bit value it continues participating If it does not have the bit value it goes into a wait state until the next 1Wire reset is detected This read two bits and write one bit pattern is then repeated for the remaining 63 bits of the ROM number see Table 2 In this way the search algorithm forces all but one device to go into this wait state At the end of one pass the ROM number of this last device is known On subsequent passes of the search a different path or branch is taken to find the other device ROM numbers Note that this document refers to the bit position in the ROM number as bit 1 least significant to bit 64 most significant This convention was used instead of bit 0 to bit 63 for convenience to allow initialization of discrepancy counters to 0 for later parisons On examination of Table 1 it is obvious that if all of the participating devices have the same value in a bit position then there is only one choice for the branch path to be taken The condition where no devices are participating is an atypical situation that may arise if the device being discovered is removed from the 1 Wire during the search If this situation arises then the search should be terminated and a new search could be done starting with a 1Wire reset Table 3 Wire Master and Slave Search Sequence Master Slave 1Wire reset stimulus Produce presence pulse Write search mand normal or alarm Each slave readies for search Read AND of bit 1 Each slave sends bit 1 of its ROM number Read AND of plement bit 1 Each slave