【導讀】太陽能作為當前人類最理想環(huán)保的新能源之一，己經得到人類越來越廣泛的應用。光伏并網逆變器是太陽能并網發(fā)電系統中必不可少的設備之一。并送入電網的設備。按照不同的標準光伏并網逆變器的拓撲結構分為很多種，本文介紹了。一種工頻隔離型光伏并網逆變器。差為零，又保證了逆變器良好的輸出波形。最后，采用TI公司的TMS320LF2407A作為主控芯片，完成了預期的設計。課題的研究背景與意義·····················&#183

　　

【正文】 CONTROLLERS The TMS320LF240x and TMS320LC240x devices, new members of the ‘24x family of digital signal processor (DSP) controllers, are part of the C2021 platform of fixedpoint DSPs. The ‘240x devices offer the enhanced TMS320 architectural design of the ‘C2xx core CPU for lowcost, lowpower, highperformance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single chip DSP controller. While codepatible with the existing ‘24x DSP controller devices, the ‘240x offers increased processing performance (30 MIPS) and a higher level of peripheral integration. See the TMS320x240x device summary section for devicespecific features. The ‘240x family offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points required by various applications. Flashbased devices of up to 32K words offer a reprogrammable solution useful for: ? Applications requiring field programmability upgrades. ? Development and initial prototyping of applications that migrate to ROMbased devices. Flash devices and corresponding ROM devices are fully pintopin patible. Note that flashbased devices contain a 256word boot ROM to facilitate incircuit programming. All ‘240x devices offer at least one event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include centered and/or edgealigned PWM generation, programmable deadband to prevent shootthrough faults, and synchronized analogtodigital conversion. Devices with dual event managers enable multiple motor and/or converter control with a single ?240x DSP controller. 28 The high performance, 10bit analogtodigital converter (ADC) has a minimum conversion time of 500 ns and offers up to 16 channels of analog input. The auto sequencing capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead. A serial munications interface (SCI) is integrated on all devices to provide asynchronous munication to other devices in the system. For systems requiring additional munication interfaces。 the ‘2407, ‘2406, and ‘2404 offer a 16bit synchronous serial peripheral interface (SPI). The ‘2407 and ‘2406 offer a controller area work (CAN) munications module that meets specifications. To maximize device flexibility, functional pins are also configurable as general purpose inputs/outputs (GPIO). To streamline development time, JTAGpliant scanbased emulation has been integrated into all devices. This provides nonintrusive realtime capabilities required to debug digital control systems. A plete suite of code generation tools from C pilers to the industrystandard Code Composerdebugger supports this family. Numerous third party developers not only offer devicelevel development tools, but also systemlevel design and development support. PERIPHERALS The integrated peripherals of the TMS320x240x are described in the following subsections: ? Two eventmanager modules (EVA, EVB) ? Enhanced analogtodigital converter (ADC) module ? Controller area work (CAN) module ? Serial munications interface (SCI) module ? Serial peripheral interface (SPI) module ? PLLbased clock module ? Digital I/O and shared pin functions ? External memory interfaces (‘LF2407 only) ? Watchdog (WD) timer module Event manager modules (EVA, EVB) 29 The eventmanager modules include generalpurpose (GP) timers, fullpare/PWM units, capture units, and quadratureencoder pulse (QEP) circuits. EVA‘s and EVB‘s timers, pare units, and capture units function identically. However, timer/unit names differ for EVA and EVB. Table 1 shows the module and signal names used. Table 1 shows the features and functionality available for the eventmanager modules and highlights EVA nomenclature. Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, pare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ. Table 1. Module and Signal Names for EVA and EVB EVENT MANAGER MODULES EVA MODULE SIGNAL EVB MODULE SIGNAL GP Timers Timer 1 Timer 2 T1PWM/T1CMP T2PWM/T2CMP Timer 3 Timer 4 T3PWM/T3CMP T4PWM/T4CMP Compare Units Compare 1 Compare 2 Compare 3 PWM1/2 PWM3/4 PWM5/6 Compare 4 Compare 5 Compare 6 PWM7/8 PWM9/10 PWM11/12 Capture Units Capture 1 Capture 2 Capture 3 CAP1 CAP2 CAP3 Capture 4 Capture 5 Capture 6 CAP4 CAP5 CAP6 QEP QEP1 QEP2 QEP1 QEP2 QEP3 QEP4 QEP3 QEP4 External Inputs Direction External Clock TDIRA TCLKINA Direction External Clock TDIRB TCLKINB 30 31 Generalpurpose (GP) timers There are two GP timers: The GP timer x (x = 1 or 2 for EVA。 x = 3 or 4 for EVB) includes: ? A 16bit timer, up/downcounter, TxCNT, for reads or writes ? A 16bit timerpare register, TxCMPR (doublebuffered with shadow register), for reads or writes ? A 16bit timerperiod register, TxPR (doublebuffered with shadow register), for reads or writes ? A 16bit timercontrol register,TxCON, for reads or writes ? Selectable internal or external input clocks ? A programmable prescaler for internal or external clock inputs ? Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer pare, and period interrupts ? A selectable direction input pin (TDIR) (to count up or down when directional up/downcount mode is selected) The GP timers can be operated independently or synchronized with each other. The pare register associated with each GP timer can be used for pare function and PWMwaveform generation. There are three continuous modes of operations for each GP timer in up or up/downcounting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other eventmanager submodules: GP timer 1 for all the pares and PWM circuits, GP timer 2/1 for the capture units and the quadraturepulse counting operations. Doublebuffering of the period and pare registers allows programmable change of the timer (PWM) period and the pare/PWM pulse width as needed. Fullpare units There are three fullpare units on each event manager. These pare units use GP timer1 as the time base and generate six outputs for pare and PWMwaveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The pare registers of the pare units are doublebuffered, allowing programmable change of the pare/PWM pulse widths as needed. Programmable deadband generator The deadband generator circuit includes three 8bit counters and