【導(dǎo)讀】幅度，頻率不變。文中對其軟，硬件的設(shè)計作了較為詳盡的闡述。描述了系統(tǒng)硬件工作原?？诩夹g(shù)和各個接口模塊的功能及工作過程。闡述了與本設(shè)計有關(guān)的各個接口芯片的功能及。本設(shè)計是以單片機(jī)的基本語言匯編語言來進(jìn)行軟件設(shè)計，指令的執(zhí)行速度快，節(jié)。為了便于擴(kuò)展和更改，軟件的設(shè)計采用模塊化結(jié)構(gòu)，使程序設(shè)計的邏輯關(guān)系。更加簡潔清晰，使硬件在軟件的控制下協(xié)調(diào)運作。起來，為系統(tǒng)的調(diào)試也帶來了很大方便。目前DDS廣泛應(yīng)用于接收機(jī)本振、信號發(fā)生器、儀器、通信系統(tǒng)、雷達(dá)系統(tǒng)等，目前相關(guān)的資料上有很多移相電路，應(yīng)。用于不同要求的各種設(shè)計中，但在這些電路中所起到的作用卻基本相同。多種多樣的，大致可以分為模擬式移相計和數(shù)字式移相計兩類。因此，在現(xiàn)實的生產(chǎn)中不被提倡其應(yīng)用也隨之減少。但其測量的精度高，失真度小，電路設(shè)計相對于模擬。本設(shè)計介紹的基于單片機(jī)AT89C51控制的數(shù)字移相計，采用環(huán)。形隊列實現(xiàn)信號波形的任意相位的移動，并且保持波形的幅度，頻率不變。

　　

【正文】 ses 64KB ROM and 64KB RAM High– speed architecture – 4 clocks/machine cycle (8032=12) – DC to 33 MHz (DS80C320) – DC to 18 MHz (DS80C323) – Single– cycle instruction in 121 ns – Uses less power for equivalent work – Dual data pointer – Optional variable length MOVX to access fast/slow RAM/peripherals High integration controller includes: – Power– fail reset – Programmable Watchdog timer – Early– warning power– fail interrupt Two full– duplex hardware serial ports 13 total interrupt sources with six external Available in 40– pin DIP, 44– pin PLCC and TQFP DESCRIPTION The DS80C320/DS80C323 is a fast 80C31/80C32 patible microcontroller. Wasted clock and memory cycles have been removed using a redesigned processor core. As a result, every 8051 instruction is executed between and 3 times faster than the original for the same crystal speed. Typical applications will see a speed improvement of times using the same code and same crystal. The DS80C320 offers a maximum crystal rate of 33 MHz, resulting in apparent execution speeds of MHz (approximately ). The DS80C320/DS80C323 is pin patible with all three packages of the standard 80C32 and offers the same timer/counters, serial port, and I/O ports. In short, the device is extremely familiar to 8051 users but provides the speed of a 16– bit processor. The DS80C320 provides several extras in addition to greater speed. These include a second full hardware serial port, seven additional interrupts, programmable watchdog timer, power– fail interrupt and reset. The device also provides dual data pointers (DPTRs) to speed block data memory moves. It can also adjust the speed of off– chip data memory access to between two and nine machine cycles for flexibility in selecting memory and peripherals. The DS80C320 operating voltage ranges from to , making it ideal as a high– performance upgrade to existing 5V systems. For applications in which power consumption is critical, the DS80C323 offers the same feature set as the DS80C320, but SIGNAL NAME DESCRIPTION 40 44 38 VCC VCC – +5V. 20 22, 23 16, 17 GND GND – Digital circuit ground. 9 10 4 RST RST – Input. The RST input pin contains a schmitt voltage input to recognize external active high Reset inputs. The pin also employs an internal pull– down resistor to allow for a bination of wired OR external Reset sources. An RC is not required for power– up, as the device provides this function internally. 18 19 20 21 14 15 XTAL2 XTAL1 XTAL1, XTAL2 – The crystal oscillator pins XTAL1 and XTAL2 provide support for parallel resonant, AT cut crystals. XTAL1 acts also as an input in the event that an external clock source is used in place of a crystal. XTAL2 serves as the output of the crystal amplifier. 29 32 26 PSEN PSEN – Output. The Program Store Enable output. This signal is monly connected to external ROM memory as a chip enable. PSEN will provide an active low pulse width of XTAL1 cycles with a period of four XTAL1 cycles. PSEN is driven high when data memory (RAM) is being accessed through the bus and during a reset condition. 30 33 27 ALE ALE – Output. The Address Latch Enable output functions as a clock to latch the external address LSB from the multiplexed address/data bus. This signal is monly connected to the latch enable of an external 373 family transparent latch. ALE has a pulse width of XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the device is in a Reset condition. 39 43 37 38 42 36 AD0 AD1 AD0– 7 (Port 0) – I/O. Port 0 is the multiplexed address/data bus. During the time when ALE is high, the LSB of a memory address is ALE falls, the port transitions to a bidirectional data bus. This bus is used to read external ROM and read/write external RAM memory or peripherals. The Port 0 has no true port latch and can not be written directly by software. The reset condition of Port 0 is high. No pull– up resistors are needed. 1– 8 2– 9 40– 44 1– 3 – Port 1 – I/O. Port 1 functions as both an 8– bit bidirectional I/O port and an alternate functional interface for Timer 2 I/O, new External Interrupts, and new Serial Port 1. The reset condition of Port 1 is with all bits at a logic 1. In this state, a weak pull– up holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overe the weak pull– up. When software writes a 0 to any port pin, the device will activate a strong pull– down that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pull– up. Once the momentary strong driver turns off, the port once again bees the output high (and input) state. Port Alternate Function T2 External I/O for Timer/Counter 2 T2EX Timer/Counter 2 Capture/Reload Trigger RXD1 Serial Port 1 Input TXD1 Serial Port 1 Output INT2 External Interrupt 2 (Positive Edge Detect) INT3 External Interrupt 3 (Negative Edge Detect) INT4 External Interrupt 4 (Positive Edge Detect) INT5 External Interrupt 5 (Negative Edge Detect) DESCRIPTION A15– A8 (Port 2) – Output. Port 2 serves as the MSB for external addressing. is A15 and is A8. The device will automatically place the MSB of an address on P2 for external ROM and RAM access. Although Port 2 can be accessed like an ordinary I/O port, the value stored on the Port 2 latch will never be seen on the pins (due to memory access). Therefore writing to Port 2, in software is only useful for the instructions MOVX A, @Ri or MOVX @Ri, A. These instructions use the Port 2 internal latch to supply the external address MSB. In this case, the Port 2 latch value will be supplied as the address information. Port 3 – I/O. Port 3