【正文】 ell 8051 UART CCDPP RAM EEPROM SOC 29 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2023 Vahid/Givargis Microcontroller ? Synthesizable version of Intel 8051 available – Written in VHDL – Captured at register transfer level (RTL) ? Fetches instruction from ROM ? Decodes using Instruction Decoder ? ALU executes arithmetic operations – Source and destination registers reside in RAM ? Special data movement instructions used to load and store externally ? Special program generates VHDL description of ROM from output of C piler/linker To External Memory Bus Controller 4K ROM 128 RAM Instruction Decoder ALU Block diagram of Intel 8051 processor core 30 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2023 Vahid/Givargis UART ? UART in idle mode until invoked – UART invoked when 8051 executes store instruction with UART’s enable register as target address ? Memorymapped munication between 8051 and all singlepurpose processors ? Lower 8bits of memory address for RAM ? Upper 8bits of memory address for memorymapped I/O devices ? Start state transmits 0 indicating start of byte transmission then transitions to Data state ? Data state sends 8 bits serially then transitions to Stop state ? Stop state transmits 1 indicating transmission done then transitions back to idle mode invoked I = 8 I 8 Idle: I = 0 Start: Transmit LOW Data: Transmit data(I), then I++ Stop: Transmit HIGH FSMD description of UART 31 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2023 Vahid/Givargis CCDPP ? Hardware implementation of zerobias operations ? Interacts with external CCD chip – CCD chip resides external to our SOC mainly because bining CCD with ordinary logic not feasible ? Internal buffer, B, memorymapped to 8051 ? Variables R, C are buffer’s row, column indices ? GetRow state reads in one row from CCD to B – 66 bytes: 64 pixels + 2 blackedout pixels ? ComputeBias state putes bias for that row and stores in variable Bias ? FixBias state iterates over same row subtracting Bias from each element ? NextRow transitions to GetRow for repeat of process on next row or to Idle state when all 64 rows pleted C = 64 C 64 R = 64 C = 66 invoked R 64 C 66 Idle: R=0 C=0 GetRow: B[R][C]=Pxl C=C+1 ComputeBias: Bias=(B[R][11] + B[R][10]) / 2 C=0 NextRow: R++ C=0 FixBias: B[R][C]=B[R][C]Bias FSMD description of CCDPP 32 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2023 Vahid/Givargis Connecting SOC ponents ? Memorymapped – All singlepurpose processors and RAM are connected to 8051’s memory bus ? Read – Processor places address on 16bit address bus – Asserts read control signal for 1 cycle – Reads data from 8bit data bus 1 cycle later – Device (RAM or SPP) detects asserted read control signal – Checks address – Places and holds requested data on data bus for 1 cycle ? Write – Processor places address and data on address and data bus – Asserts write control signal for 1 clock cycle – Device (RAM or SPP) detects asserted write control signal – Checks address bus – Reads and stores data from data bus 33 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2023 Vahid/Givargis Software ? Systemlevel model provides majority of code – Module hierarchy, procedure names, and main program unchanged ? Code for UART and CCDPP modules must be redesigned – Simply replace with memory assignments ? xdata used to load/store variables over external memory bus ? _at_ specifies memory address to store these variables ? Byte sent to U_TX_REG by processor will invoke UART ? U_STAT_REG used by UART to indicate its ready for next byte – UART may be much slower than processor – Similar modification for CCDPP code ? All other modules untouched static unsigned char xdata U_TX_REG _at_ 65535。 static unsigned char xdata U_STAT_REG _at_ 65534。 void UARTInitialize(void) {} void UARTSend(unsigned char d) { while( U_STAT_REG == 1 ) { /* busy wait */ } U_TX_REG = d。 } Rewritten UART module include static FILE *outputFileHandle。 void UartInitialize(const char *outputFileName) { outputFileHandle = fopen(outputFileName, w)。 } void UartSend(char d) { fprintf(outputFileHandle, %i\n, (int)d)。 } Original code from systemlevel model 34 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2023 Vahid/Givargis Analysis ? Entire SOC tested on VHDL simulator – Interprets VHDL descriptions and functionally simulates execution of system ? Recall program code translated to VHDL description of ROM – Tests for correct functionality – Measures clock cycles to process one image (performance) ? Gatelevel description obtained through synthesis – Synthesis tool like piler for SPPs – Simulate gatelevel models to obtain data for power analysis ? Number of times gates switch from 1 to 0 or 0 to 1 – Count number of gates for chip area Power VHDL simulator VHDL VHDL VHDL Execution time Synthesis tool gates gates gates Sum gates Gate level simulator Power equation Chip area Obtaining design metrics of interest 35 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2023 Vahid/Givargis Implementation 2: Microcontroller and CCDPP ? Analysis of implementation 2 – Total execution time for processing one image: ? seconds – Power consumption: ? watt – Energy consumption: ? joule ( s x watt) – Total chip area: ? 98,000 gates 36 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2023 Vahid/Givargis Imp