【導(dǎo)讀】精品-基于FPGA與單片機(jī)通訊的LCD顯示模塊設(shè)計(jì)畢。在數(shù)字電路技術(shù)高度發(fā)展的今天基于FPGA單片機(jī)的產(chǎn)品無處不在液晶顯示。也成為現(xiàn)代顯示器的主流產(chǎn)品LCD液晶顯示已經(jīng)是人機(jī)交互界面得以實(shí)現(xiàn)的關(guān)。鍵手段本文對基于FPGA與單片機(jī)通信及單片機(jī)驅(qū)動(dòng)LCD液晶顯示器系統(tǒng)進(jìn)行了。本文簡要介紹了用單片機(jī)作驅(qū)動(dòng)控制器的GDM12864A的基本原理漢字的顯。示原理以及單片機(jī)的原理闡述了基于51系列單片機(jī)的LCD液晶顯示器的并行方。式的接口電路設(shè)計(jì)方法對驅(qū)動(dòng)電路的應(yīng)用方法加以研究還詳細(xì)說明了其驅(qū)動(dòng)程。序相關(guān)部分的設(shè)計(jì)步驟并給出了相關(guān)代碼。本設(shè)計(jì)的重點(diǎn)是用單片機(jī)驅(qū)動(dòng)控制LCD顯示器接受來自FPGA發(fā)的信號(hào)根據(jù)。目的就是將LCD用到實(shí)驗(yàn)里不止做簡單的幾個(gè)漢字顯示讓它顯示我們試驗(yàn)中。在本課題中FPGA只傳輸一些在試驗(yàn)中比較簡單的數(shù)字信號(hào)所以在寫驅(qū)動(dòng)程。滿足我們的要求通過本課題設(shè)計(jì)能解決試驗(yàn)箱GW48-SOPC上LCD一直不被利用的。§11開發(fā)背景及意義8. §13系統(tǒng)方案流程圖9. §222FPGA系列芯片介紹14. §32FPGA嵌入式存儲(chǔ)器模塊28. §52單片機(jī)驅(qū)動(dòng)測試40

　　

【正文】 計(jì) 提供了一種有效的方法在眾多的應(yīng)用領(lǐng)域中 少量改動(dòng)程序和字符即可滿足用戶的不同需求本文所述的基于 C51 匯編語言的單片機(jī)控制 LCD 驅(qū)動(dòng)器的方法是在實(shí)際工作中總結(jié)出的僅從應(yīng)用角度介紹了控制的原理沒有詳細(xì)介紹工作模式命令格式及圖形算法我們認(rèn)為理解了控制顯示原理再參考數(shù)據(jù)手冊就很容易掌握其應(yīng)用由于該方法可移植性很強(qiáng)因此稍做修改就可應(yīng)用于其他實(shí)際工程項(xiàng)目方便設(shè)計(jì)開發(fā) 本文介紹了 GDM12864A 液晶顯示模塊的性能特點(diǎn)和工作原理 以 51 單片機(jī)為例討論了微控制器和 GDM12864A 液晶控制模塊的串行控制接口實(shí)現(xiàn)方法 并給出了具體實(shí)現(xiàn)電路和顯示漢字及圖形的相關(guān)程序本文討論了用軟件模擬并行總線控制 LCM 的方法 電路簡單使用方便具有很好的通用性 參考文獻(xiàn) 李維堤 郭強(qiáng)液晶顯示應(yīng)用技術(shù) [M]北京 電子工業(yè)出版社 1996 馬忠梅單片機(jī)的 C 語言應(yīng)用程序設(shè)計(jì) [M]北京 北京航空航天大學(xué) 出版社 2020 北京清華蓬遠(yuǎn)公司 SED1335 控制器圖形液晶顯示模塊使用手冊 [Z] 北京 清華蓬遠(yuǎn)公司 2020 張 毅剛 等 MCS 51 單片機(jī)應(yīng)用設(shè)計(jì) [M]哈爾濱 哈爾濱工業(yè)大學(xué)出版社 1997 陳 鋮宋曙春 基于 T6963C 控制器的液晶顯示模塊組成原理 [ J ] 信息工程大學(xué)學(xué)報(bào) 2020 4 3 26229 王建校 51 系列單片機(jī)及 C51 程序設(shè)計(jì) [M ] 北京科學(xué)出版社 2020 胡凱張穎超生化分析儀的設(shè)計(jì)及與 PC 機(jī)的通信 [J]微計(jì)算機(jī)信息202022 4 1 208 209 皮大能南光群 JHD161A LCD 顯示器與 PIC16F877 單片機(jī)連接 [J]微計(jì)算機(jī)信息 202020 10 94 95 馬鴻文基于 AT89C52 單片機(jī)的自動(dòng)存取柜的設(shè)計(jì)與實(shí)現(xiàn) [J]微計(jì)算機(jī)信息 202022 1 2 101 103 李維諟郭強(qiáng)液晶顯示應(yīng)用技術(shù) [M] 北京 電子工業(yè)出版社 20206 李學(xué)海 PIC 單片機(jī)使用教程 提高篇 [M] 北京航空航天大學(xué)出版社 20203 胡漢才 單片機(jī)原理及系統(tǒng)設(shè)計(jì) 北京清華大學(xué)出版社 2020 LCM12832ZK 和 C8051F124 接口 [J]微計(jì)算機(jī)信息 20205 李崇德現(xiàn)代數(shù)字存貯示波器原理及應(yīng)用北京電子工業(yè)出版社 198933 37 霍孟友單片機(jī)原理與應(yīng)用 [M ]北京機(jī)械工業(yè)出版社 2020 David RCoelho The VHDL handbook KLUWER Academic Pubishers1989 IEEE Standard VHDL Language Reference Manual IEEE Press1987 VHDL Language Reference GuideAlde INCHenderson NV USA1999 VHDL Referenc GuideXilinx IncSan Jose USA1998 Stephen BrownZvonko VranesicFundmentl of Digital with VHDL DesignMcGrawHill Professional2020 致 謝 本設(shè)計(jì)我是在外面公司實(shí)習(xí)期間做的首先我很感謝齊老師給我的幫助設(shè)計(jì)中我遇到了很多問題每次通過網(wǎng)絡(luò)向齊老師請教齊老師都很細(xì)心的給我講解這幾年里在學(xué)習(xí)方面齊老師給了我很大的教導(dǎo)在工作中深深的感到平時(shí)學(xué)習(xí)的東西的重要老師曾經(jīng)告訴我們做事要認(rèn)真謹(jǐn)慎踏實(shí)這些在人生中將教導(dǎo)我們一生在論文完成之際特向齊老師表示由衷的感謝并祝 齊老師身體健康心想事成 同時(shí)也要感謝我所在公司的項(xiàng)目經(jīng)理他讓我知道了在工作中要注意的問題在畢業(yè)設(shè)計(jì)中也感謝他給與我的支持和幫助 感謝所有在我畢業(yè)設(shè)計(jì)中給我?guī)椭耐瑢W(xué)愿大家在今后的人生道路中一切順利 二零零八年六月于河南科技大學(xué) 外文資料原文 AT24C01 The AT24C01 provides 1024 bits of serial electrically erasable and programmable read only memory EEPROM anized as 128 words of 8 bits each The device is optimized for use in many industrial and mercial applications where low power and low voltage operation are essential The AT24C01 is available in space saving 8pin PDIP 8pin TSSOP and 8pin JEDEC SOIC packages and is accessed via a 2wire serial interface In addition the entire family is available in 27V 27V to 55V and 18V 18V to 55V versions Block Diagram Pin Description SERIAL CLOCK SCL The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each deviceSERIAL DATA SDA The SDA pin is bidirectional for serial data transfer This pin isopendrain driven and may be wireORed with any number of other opendrain or open collector devicesMemory Organization AT24C01 1K SERIAL EEPROM Internally anized with 128 pages of 1 byte eachThe 1K requires a 7bit data word address for random word addressing Pin CapacitanceApplicable over remended operating range from TA 25176。C f 10 MHz VCC 18V DC Characteristics Applicable over remended operating range from TAI 40176。Cto85176。C VCC 18V to 55V TAC 0176。Cto70176。CVCC 18V to 55V unless otherwise noted AC Characteristics Applicable over remended operating range from TA 40176。Cto85176。C VCC 18V to 55V CL 1 TTL Gate and100 pF unless otherwise noted Device Operation CLOCK and DATA TRANSITIONS The SDA pin is normally pulled high with an external device Data on the SDA pin may change only during SCL low time periods refer toData Validity timing diagram Data changes during SCL high periods will indicate a start or stop condition as defined below START CONDITION A hightolow transition of SDA with SCL high is a start conditionwhich must precede any other mand refer to Start and Stop Definition timing diagram STOP CONDITION A lowtohigh transition of SDA with SCL high is a stop condition which terminates all munications After a read sequence the stop mand will place the EEPROM in a standby power mode refer to Start and Stop Definition timing diagram ACKNOWLEDGE All addresses and data words are serially transmitted to and from the EEPROM in 8bit words Any device on the system bus receiving data when municating with the EEPROM must pull the SDA bus low to acknowledge that it has successfully received each word This must happen during the ninth clock cycle after each word received and after all other system devices have freed the SDA bus The EEPROM will likewise acknowledge by pulling SDA low after receiving each address or data word refer to Acknowledge Response from Receiver timing diagram STANDBY MODE The AT24C01 features a low power standby mode which is enabled a upon powerup and b after the receipt of the STOP bit and the pletion of any internal operations MEMORY RESET After an interruption in protocol power loss or system reset any 2wire part can be reset by following these steps a Clock up to 9 cycles b look for SDA high in each cycle while SCL is high and then c create a start condition as SDA is high Write Operations BYTE WRITE Following a start condition a write operation requires a 7bit data word address and a low write bit Upon receipt of this address the EEPROM will again respond with a zero and then clock in the first 8bit data word Following receipt of the 8bit data word the EEPROM will output a zero and the addressing device such as a microcontroller must terminate the write sequence with a stop condition At this time the EEPROM enters an internallytimed write cycle to the nonvolatile memory All inputs are disabled during this write cycle tWR and the EEPROM will not respond until the write is plete refer to Figure 1 PAGE WRITE The AT24C01 is capable of a 4byte page write A page write is initiated the same as a byte write but the microcontroller does not send a stop condition after the first data word is clocked in Instead after the EEPROM acknowledges receipt of th