【正文】 SegA (uchar value){ uchar *Flash_ptr。 // Flash pointer uint i。 Flash_ptr = (uchar *) 0x1080。 // Initialize Flash pointer FCTL1 = FWKEY + ERASE。 // Set Erase bit FCTL3 = FWKEY。 // Clear Lock bit *Flash_ptr = 0。 // Dummy write to erase Flash segment FCTL1 = FWKEY + WRT。 // Set WRT bit for write operation for (i=0。 i128。 i++) { *Flash_ptr++ = value。 // Write value to flash } FCTL1 = FWKEY。 // Clear WRT bit FCTL3 = FWKEY + LOCK。 // Set LOCK bit}void copy_A2B (void){ uchar *Flash_ptrA。 // Segment A pointer uchar *Flash_ptrB。 // Segment B pointer uint i。 Flash_ptrA = (uchar *) 0x1080。 // Initialize Flash segment A pointer Flash_ptrB = (uchar *) 0x1000。 // Initialize Flash segment B pointer FCTL1 = FWKEY + ERASE。 // Set Erase bit FCTL3 = FWKEY。 // Clear Lock bit *Flash_ptrB = 0。 // Dummy write to erase Flash segment B FCTL1 = FWKEY + WRT。 // Set WRT bit for write operation for (i=0。 i128。 i++) { DataBuffer[i] = *Flash_ptrA++。 *Flash_ptrB++ = DataBuffer[i]。 // Copy value segment A to segment B } FCTL1 = FWKEY。 // Clear WRT bit FCTL3 = FWKEY + LOCK。 // Set LOCK bit}//******************************************************************************// MSPFET430P140 Demo USART0, UltraLow Pwr UART 2400 Echo ISR, 32kHz ACLK//// Description: Echo a received character, RX ISR used. In the Mainloop UART0// is made ready to receive one character with interrupt active. The Mainloop// waits in LPM3. The UART0 ISR forces the Mainloop to exit LPM3 after// receiving one character which echo39。s back the received character.// ACLK = UCLK0 = LFXT1 = 32768, MCLK = SMCLK = DCO~ 800k// Baud rate divider with 32768hz XTAL @2400 = 32768Hz/2400 = (000Dh)// //* An external watch crystal is required on XIN XOUT for ACLK *// //// MSP430F149// // /|\| XIN|// | | | 32kHz// |RST XOUT|// | |// | |// | | 2400 8N1// | |////// M. Buccini// Texas Instruments Inc.// Feb 2005// Built with IAR Embedded Workbench Version: //******************************************************************************include include void main(void){ BoardConfig(0xb8)。 WDTCTL = WDTPW + WDTHOLD。 // Stop WDT P3SEL |= 0x30。 // ,5 = USART0 TXD/RXD ME1 |= UTXE0 + URXE0。 // Enable USART0 TXD/RXD UCTL0 |= CHAR。 // 8bit character UTCTL0 |= SSEL0。 // UCLK = ACLK UBR00 = 0x0D。 // 32k/2400 UBR10 = 0x00。 // UMCTL0 = 0x6B。 // Modulation UCTL0 amp。= ~SWRST。 // Initialize USART state machine IE1 |= URXIE0。 // Enable USART0 RX interrupt// Mainloop for (。) { _BIS_SR(LPM3_bits + GIE)。 // Enter LPM3 w/interrupt while (!(IFG1 amp。 UTXIFG0))。 // USART0 TX buffer ready? TXBUF0 = RXBUF0。 // RXBUF0 to TXBUF0 }}// UART0 RX ISR will for exit from LPM3 in Mainlooppragma vector=UART0RX_VECTOR__interrupt void usart0_rx (void){ _BIC_SR_IRQ(LPM3_bits)。 // Clear LPM3 bits from 0(SR)}//******************************************************************************// MSPFET430P140 Demo USART0, UltraLow Pwr UART 9600 Echo ISR, 32kHz ACLK//// Description: Echo a received character, RX ISR used. In the Mainloop UART0// is made ready to receive one character with interrupt active. The Mainloop// waits in LPM3. The UART0 ISR forces the Mainloop to exit LPM3 after// receiving one character which echo39。s back the received character.// ACLK = UCLK0 = LFXT1 = 32768, MCLK = SMCLK = DCO~ 800k// Baud rate divider with 32768hz XTAL @9600 = 32768Hz/9600 = (0003h 4Ah )// //* An external watch crystal is required on XIN XOUT for ACLK *// //// MSP430F149// // /|\| XIN|// | | | 32kHz// |RST XOUT|// | |// | |// | | 9600 8N1// | |////// M. Buccini// Texas Instruments Inc.// Feb 2005// Built with IAR Embedded Workbench Version: //******************************************************************************include include void main(void){ BoardConfig(0xb8)。 WDTCTL = WDTPW + WDTHOLD。 // Stop WDT P3SEL |= 0x30。 // ,5 = USART0 TXD/RXD ME1 |= UTXE0 + URXE0。 // Enable USART0 TXD/RXD UCTL0 |= CHAR。 // 8bit character UTCTL0 |= SSEL0。 // UCLK = ACLK UBR00 = 0x03。 // 32k/9600 UBR10 = 0x00。 // UMCTL0 = 0x4A。 // Modulation UCTL0 amp。= ~SWRST。 // Initialize USART state machine IE1 |= URXIE0。 // Enable USART0 RX interrupt// Mainloop for (。) { _BIS_SR(LPM3_bits + GI