第5章-計(jì)算機(jī)組成-資料下載頁(yè)
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【正文】 register? (Knowledge point )Solution:The size of an instruction in bits is 16. Data size is the same with that of an instruction. So 16 is the size of each data register.82. What is the size of the instruction register of the puter in Exercise 80? (Knowledge point )Solution:The size of an instruction in bits is 16. So the size of the instruction register of the puter is also 16.83. What is the size of the program counter of the puter in Exercise 80? (Knowledge point )Solution:The number of words in this puter is 1024, that is 2 raised to the power 10. So the size of the program counter of the puter is 10.84. What is the size of the data bus in Exercise 80? (Knowledge point )Solution:Data size of this puter in bits is 16. So the size of the data bus is 16.85. What is the size of the address bus in Exercise 80? (Knowledge point )Solution:The number of words in this puter is 1024, that is 2 raised to the power 10. So the the size of the address bus is 10.86. What is the minimum size of the control bus in Exercise 80? (Knowledge point )Solution:There are 2 control actions(read and write to memory) at most. So the minimum size of the control bus is 1. 87. A puter uses isolated I/O addressing. Memory has 1024 words. If each controller has 16 registers, how many controllers can be accessed by this puter? (Knowledge point )Solution:Memory has 1024 words. So the address space is 1024. Each controller has 16 registers. Then we get 64 (divide 16 by 1024)controllers which can be accessed by this puter. 88. A puter uses memorymapped I/O addressing. The address bus uses 10 lines. If memory is made of 1000 words, how many fourregister controllers can be accessed by this puter? (Knowledge point )Solution:The address bus uses 10 lines. So, the address space is 1024(2 raised to the power 10). The memory is made of 1000 words and each controller has four registers. Then we get (10241000)/4 = 6 fourregister controllers which can be accessed by this puter.
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