【正文】 { nco_table_cos nco_table_log} net {VDD VSS}set_fp_rail_constraints set_global no_routing_over_hard_macrosset_fp_rail_constraints set_ring nets {VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS} horizontal_ring_layer { METAL3 } vertical_ring_layer { METAL2 } ring_max_width 3 ring_min_width 2 ring_offset 12 extend_strap core_ringsynthesize_fp_rail nets {VDD VSS} voltage_supply synthesize_power_plan power_budget 80mit_fp_railcreate_power_straps direction vertical start_at nets {VSS VDD} layer METAL2 width 3 start_low_ends coordinate start_low_ends_coordinate 786 extend_for_multiple_connections extension_gap create_power_straps direction vertical start_at 1435 nets {VSS VDD} layer METAL2 width 3 extend_for_multiple_connections extension_gap 10preroute_instances ignore_macros ignore_cover_cells skip_bottom_side skip_top_side route_pins_on_layer METAL1 primary_routing_layer pin extend_for_multiple_connections extension_gap preroute_instances ignore_macros ignore_cover_cells skip_left_side skip_right_side route_pins_on_layer METAL2 primary_routing_layer pin extend_for_multiple_connections extension_gap preroute_instances ignore_pads ignore_cover_cells primary_routing_layer pinpreroute_standard_cells extend_for_multiple_connections extension_gap 10 connect horizontal remove_floating_pieces do_not_route_over_macros fill_empty_rows port_filter_mode off cell_master_filter_mode off cell_instance_filter_mode off voltage_area_filter_mode off route_type {P/G Std. Cell Pin Conn}set_pnet_options plete METAL3 METAL2create_fp_placement incremental allsave_mw_cel design CHIPsave_mw_cel design CHIP as design_planningPlacement腳本范例place_optCTS腳本范例set cts_enable_clock_at_hierarchical_pin trueset power_cg_auto_identify truecheck_physical_design for_ctscheck_clock_treereport_clockreport_clock skewreport_clock_tree summaryreport_constraint allset_fix_hold [all_clocks]report_qorset_max_area 0set physopt_area_critical_range clock_opt fix_hold_all_clocks no_clock_routeRoute腳本范例derive_pg_connection power_net {VDD} ground_net {VSS} power_pin {VDD} ground_pin {VSS}source ../tech/set_route_zrt_mon_options post_detail_route_redundant_via_insertion high concurrent_redundant_via_mode insert_at_high_cost concurrent_redundant_via_effort_level highroute_zrt_group all_clock_netsroute_zrt_auto set_route_zrt_detail_options diode_libcell_names ANTENNA insert_diodes_during_routing trueverify_zrt_routeroute_zrt_detail incremental true initial_drc_from_input truederive_pg_connection power_net {VDD} ground_net {VSS} power_pin {VDD} ground_pin {VSS}文件導(dǎo)出范例write_verilog unconnected_ports diode_ports wire_declaration keep_backslash_before_hiersep no_physical_only_cells write_sdf version context verilog load_delay net set_write_stream_options map_layer ../tech/ child_depth 20 flatten_viawrite_stream format gds lib_name CHIP cells {CHIP } insert_stdcell_filler cell_without_metal FILL64 FILL32 FILL16 FILL8 FILL4 FILL2 FILL1 connect_to_power {VDD} connect_to_ground {VSS}verify_zrt_routeroute_zrt_detail incremental true initial_drc_from_input truederive_pg_connection power_net {VDD} ground_net {VSS} power_pin {VDD} ground_pin {VSS}ECO腳本范例if {$ICC_ECO_FLOW == UNCONSTRAINED} { echo SCRIPTInfo: starting the unconstrained ECO flow, executing the ECO steps if {[file exists [which $ICC_ECO_NETLIST]]} { eco_netlist pare_pg by_verilog_file $ICC_ECO_NETLIST legalize_placement eco incremental route_eco } else { echo SCRIPTError can39。t perform eco, eco netlist $ICC_ECO_NETLIST can39。t be found ... }}if {$ICC_ECO_FLOW == FREEZE_SILICON} { echo SCRIPTInfo: starting the Freeze Silicon ECO flow, executing the ECO steps if {[file exists [which $ICC_ECO_NETLIST]]} { eco_netlist pare_pg freeze_silicon by_verilog_file $ICC_ECO_NETLIST place_freeze_silicon route_eco } else { echo SCRIPTError can39。t perform eco, eco netlist $ICC_ECO_NETLIST can39。t be found ... }} CONNECT P/G Connect Power amp。 Ground for nonMV and MVmode if {[file exists [which $CUSTOM_CONNECT_PG_NETS_SCRIPT]]} { source echo $CUSTOM_CONNECT_PG_NETS_SCRIPT } else { derive_pg_connection power_net $MW_POWER_NET power_pin $MW_POWER_PORT ground_net $MW_GROUND_NET ground_pin $MW_GROUND_PORT if {!$ICC_TIE_CELL_FLOW} {derive_pg_connection power_net $MW_POWER_NET ground_net $MW_GROUND_NET tie} }if { [check_error verbose] != 0} { echo SCRIPTError, flagging ... }if {$ICC_REPORTING_EFFORT != OFF } { redirect tee file $REPORTS_DIR/$ {report_clock_tree –summary } 。 global skew report redirect file $REPORTS_DIR/$ {report_clock_timing type skew} 。 local skew report}if {$ICC_REPORTING_EFFORT != OFF } { redirect tee file $REPORTS_DIR/$ {report_qor} redirect file $REPORTS_DIR/$ {report_constraints}}if {$ICC_REPORTING_EFFORT != OFF } { redirect file $REPORTS_DIR/$ {report_timing capacitance transition_time input_pins nets delay max} redirect file $REPORTS_DIR/$ {report_timing capacitance transition_time input_pins nets delay min} }save_mw_cel as $ICC_POST_ECO_CELif {$ICC_REPORTING_EFFORT != OFF } { create_qor_snapshot clock_tree name $ICC_POST_ECO_CEL redirect file $REPORTS_DIR/$ {report_qor_snapshot no_display}}VCS學(xué)習(xí)筆記DFT學(xué)習(xí)筆記Tcl語(yǔ)言學(xué)習(xí)筆記Perl語(yǔ)言學(xué)習(xí)筆記時(shí)序?qū)W習(xí)筆記基本概念靜態(tài)時(shí)序分析的前提是同步邏輯設(shè)計(jì)。關(guān)鍵路徑通常是指通路邏輯電路中，組合邏輯延遲最大的路徑。也就是說(shuō)關(guān)鍵路徑是對(duì)設(shè)計(jì)性能起決定性影響的時(shí)序路徑。設(shè)DFF1的延遲為T(mén)cq，組合電路Comb的延遲為T(mén)c，DFF2的建立時(shí)間為T(mén)setup，那么這個(gè)電路的時(shí)鐘周期為：Tclk=Tcq+Tc+Tsetup(如果Tclk小于這個(gè)值就有可能對(duì)數(shù)據(jù)采樣一次以上，這便產(chǎn)生了數(shù)據(jù)紊亂)。如果DFF2的保持時(shí)間很長(zhǎng)而組合電路的延遲很小，那么可能數(shù)據(jù)在一個(gè)周期內(nèi)穿過(guò)兩個(gè)時(shí)序單元，