【導(dǎo)讀】基于EDA技術(shù)交通信號燈設(shè)計。1EDA技術(shù)及VHDL語言介紹。CAD計算機(jī)輔助設(shè)計CAM計算機(jī)輔助制造CAT計算機(jī)輔助測試和CAE計算機(jī)輔助。工程的概念發(fā)展而來的EDA技術(shù)是以計算機(jī)為工具根據(jù)硬件描述語言HDL. 綜合及優(yōu)化布局布線仿真以及對于特定目標(biāo)芯片的適配編譯和編程下載等工作。典型的EDA工具中必須包含兩個特殊的軟件包即綜合器和適配器綜合器的功能。就是將設(shè)計者在EDA平臺上完成的針對某個系統(tǒng)項目的HDL原理圖或狀態(tài)圖形描。述針對給定的硬件系統(tǒng)組件進(jìn)行編譯優(yōu)化轉(zhuǎn)換和綜合最終獲得我們欲實現(xiàn)功能。適配器的功能是將由綜合器產(chǎn)生的王表文件配置與指定的目標(biāo)器件中產(chǎn)生最終。結(jié)構(gòu)和連接方式設(shè)計者可利用HDL程序來描述所希望的電路系統(tǒng)規(guī)定器件結(jié)構(gòu)。件目前就FPGACPLD開發(fā)來說比較常用和流行的HDL主要有ABEL-HDLAHDL和VHDL. 從目前的EDA技術(shù)來看其發(fā)展趨勢是政府重視使用普及應(yīng)用廣泛工具多樣軟件。設(shè)計活動以應(yīng)對亞太地區(qū)其它EDA市場的競爭在EDA軟件開發(fā)方面目前主要集中

　　

【正文】 butt 1 then recount 1 state e sign_state 1XXXXXXXXXX1 else recount 0 state d end if end if when e if a_m 1 then if next_state 1 then recount 1 state f sign_state 1XXXXXXXXXX1 else recount 0 state e end if elsif a_m 0 then if h_butt 1 then recount 1 state f sign_state 1XXXXXXXXXX1 else recount 0 state e end if end if when f if a_m 1 then if next_state 1 then recount 1 state a sign_state 1XXXXXXXXXX1 else recount 0 state f end if elsif a_m 0 then if h_butt 1 then recount 1 state a sign_state 1XXXXXXXXXX1 else recount 0 state f end if end if when others state a end case end if end if end process end 閃爍電路程序 library ieee use ieeestd_logic_1164all use ieeestd_logic_unsignedall entity ssmk is port clkresetclk_flashholdin std_logic flash in std_logic flash_addr in std_logic_vector 1 downto 0 dins in std_logic_vector 11 downto 0 doutout std_logic_vector 11 downto 0 end architecture art of ssmk is signal t std_logic_vector 11 downto 0 signal t_flash std_logic_vector 11 downto 0 begin process clk_flashclkholdflash_addrreset begin if reset 1 then t_flash 000000000000 elsif clkevent and clk 1 then if hold 1 then t_flash dins elsif clk_flash 1 then if flash_addr 01and flash 1then t 01XXXXXXXXXX t_flash dins xor t else t_flash dins end if elsif flash_addr 11 and flash 1 then t 01XXXXXXXXXX t_flash dins xor t else t_flash dins end if end if end process dout t_flash end 消振電路程序 library ieee use ieeestd_logic_1164all use ieeestd_logic_unsignedall entity xzdl is port resetrholdra_mrh_buttrclkrin std_logic hoqhqaq out std_logic end architecture one of xzdl is signal t2t3t4 std_logic_vector 3 downto 0 begin process resetrholdra_mrh_buttrclkr begin if resetr 1then t2 0000 t3 0000 t4 0000 elsif clkrevent and clkr 1 then if holdr 1 then if t2 0111 then t2 0000 hoq 1 else t2 t21 hoq 0 end if end if if a_mr 1then if t3 0111 then t3 0000 aq 1 else t3 t31 aq 0 end if end if if h_buttr 1 then if t4 0111 then t4 0000 hq 1 else t4 t41 hq 0 end if end if end if end process end 譯碼器程序 library ieee use ieeestd_logic_1164all entity ymq is port ainin std_logic_vector 3 downto 0 yout out std_logic_vector 6 downto 0 end architecture one of ymq is begin process ain begincase ain is when 0000 yout 0111111 when 0001 yout 0000110 when 0010 yout 1011011 when 0011 yout 1001111 when 0100 yout 1101101 when 0101 yout 1111101 when 0110 yout 0000111 when 0111 yout 1111111 when 1000 yout 1101111 when others yout 0000000 end case end process end 總體程序 library ieee use ieeestd_logic_1164all use ieeestd_logic_unsignedall entity t_center is port clockreseta_mholdh_buttin std_logic dout0out std_logic_vector 11 downto 0 out1 out2 out3 out4out std_logic_vector 3 downto 0 end entity t_center architecture art of t_center is ponent ymq is port ainin std_logic_vector 3 downto 0 yout out std_logic_vector 6 downto 0 end ponent ponent fpq is port clk_1kresetin std_logic clkclk_flash out std_logic end ponent fpq ponent jsq is port clkresetrecountholdin std_logic din1din2in std_logic_vector 7 downto 0 dout1dout2 dout3dout4 out std_logic_vector 3 downto 0 next_state out std_logic flash out std_logic end ponent jsq ponent jsqkzq is port clk in std_logic reset in std_logic recountin std_logic sign_s in std_logic_vector 11 downto 0 load1 out std_logic_vector 7 downto 0 load2 out std_logic_vector 7 downto 0 flash_addr out std_logic_vector 1 downto 0 end ponent jsqkzq ponent jtdkz is port clkreseta_mh_buttholdin std_logic next_state in std_logic recount out std_logic sign_state inout std_logic_vector 11 downto 0 end ponent jtdkz ponent ssmk is port clkresetclk_flashholdin std_logic flash in std_logic flash_addr in std_logic_vector 1 downto 0 dins in std_logic_vector 11 downto 0 doutout std_logic_vector 11 downto 0 end ponent ssmk ponent xzdl is port resetrholdra_mrh_buttrclkrin std_logic rqhoqhqaq out std_logic end ponent xzdl signal a1a2a3a4std_logic_vector 3 downto 0 signal b1b2b3b4std_logic signal s1s2std_logic signal c1c2std_logic_vector 7 downto 0 signal d2d3d4std_logic signal f0std_logic_vector 1 downto 0 signal e0std_logic_vector 11 downto 0 begin u1xzdl port map clkr clockresetr resetholdr hold h_buttr h_butta_mr a_maq b2 hq b3hoq b4 u2fpq port map clk_1k clockreset b1 clk s1clk_flash s2 u3jsq port map clk s1reset b1hold b4recount d4 din1 c1din2 c2dout1 a1dout2 a2 dout3 a3dout4 a4next_state d3flash d2 u4jsqkzq port map clk s1reset b1 recount d4 sign_s e0load1 c1load2 c2 flash_addr f0 u5jtdkz port map clk s1reset b1hold b4a_m b2h_butt b3 recount d4sign_state e0 next_state d3 u6ssmk port map clk s1reset b1clk_flash s2hold b4flash d2 dins e0dout dout0flash_addr f0 u7ymq port map ain a1yout out1 u8ymq port map ain a2yout out2 u9ymq port map ain a3yout out3 u10ymq port map ain a4yout out4