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【正文】 d low will source current (IIL) because of the pullups.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on should be strapped to VCC for internal program pin also receives the 12volt programming enable voltage(VPP) during Flash programming, for parts that require12volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Powerdown ModeIn the powerdown mode, the oscillator is stopped, and the instruction that invokes powerdown is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the powerdown mode is terminated. The only exit from powerdown is a hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.附錄B發(fā)送部分程序/***************************************************/include include //_nop_()。延時(shí)函數(shù)用typedef unsigned char uchar。typedef unsigned char uint。//數(shù)碼管顯示管腳定義sbit MISO =P1^5。sbit MOSI =P1^1。sbit SCK =P1^6。sbit CE =P1^7。sbit CSN =P1^2。sbit IRQ =P1^0。sbit TRH = P3^7。//溫濕度傳感器DHT11數(shù)據(jù)接入 unsigned char TxBuf[2]。void read_TRH()。void delay_us()。char receive()。void delay_ms(unsigned char ms)。uchar TH_data,TL_data,RH_data,RL_data,CK_data。uchar TH_temp,TL_temp,RH_temp,RL_temp,CK_temp。uchar _data,untemp,temp_h。uchar respond。//*********************************************NRF24L01*************************************define TX_ADR_WIDTH 5 // 5 uints TX address widthdefine RX_ADR_WIDTH 5 // 5 uints RX address widthdefine TX_PLOAD_WIDTH 2 // 20 uints TX payloaddefine RX_PLOAD_WIDTH 2 // 20 uints TX payloaduint const TX_ADDRESS[TX_ADR_WIDTH]= {0x34,0x43,0x10,0x10,0x01}。 //本地地址uint const RX_ADDRESS[RX_ADR_WIDTH]= {0x34,0x43,0x10,0x10,0x01}。 //接收地址//***************************************NRF24L01寄存器指令*******************************************************define READ_REG 0x00 // 讀寄存器指令define WRITE_REG 0x20 // 寫(xiě)寄存器指令define RD_RX_PLOAD 0x61 // 讀取接收數(shù)據(jù)指令define WR_TX_PLOAD 0xA0 // 寫(xiě)待發(fā)數(shù)據(jù)指令define FLUSH_TX 0xE1 // 沖洗發(fā)送 FIFO指令define FLUSH_RX 0xE2 // 沖洗接收 FIFO指令define REUSE_TX_PL 0xE3 // 定義重復(fù)裝載數(shù)據(jù)指令define NOP 0xFF // 保留//*************************************SPI(nRF24L01)寄存器地址****************************************************define CONFIG 0x0
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