【正文】 ；轉(zhuǎn)換8個(gè)控制 LCALL TESTART ；啟動(dòng)測(cè)試WAIT: JB ,MOVD ；等A/D轉(zhuǎn)換結(jié)束信號(hào) AJMP WAIT；TESTART: SETB ；測(cè)試啟動(dòng) NOP NOP CLR STEB NOP NOP CLR NOP NOP NOP NOP RET；MOVD: SETB ；取A/D轉(zhuǎn)換數(shù)據(jù) MOV A,P0 MOV @R0,A CLR INC R0 MOV A,P2 ；通道地址加1 INC A MOV P2,A CJNE A,08H,TESTEND ；等8路A/D轉(zhuǎn)換結(jié)束TESTEND: JC TESTCON CLR A ；結(jié)束恢復(fù)端口 MOV P2,A MOV A,0FFH MOV P0,A MOV P1,A MOV P3,A RET；TESTCON: LCALL TESTART LJMP WAIT；；***********************；* 按鍵檢測(cè)子程序 *；***********************；KEYWORK1: JNB ,KEY1KEYOUR: RET；KEY1: LCALL DISP ；延時(shí)消抖 JB ,KEYOUTWAIT11: JNB ,WAIT12 CPL 00H MOV R2,01H MOV R3,01H RET；WAIT12。 LCALL DISP ；釋放等待時(shí)顯示用 AJMP WAIT11。KEYWORK2: JNB ,KEY1 JNB ,KEY2 RET；KEY2: LCALL DISP ；延時(shí)消抖用 JB ,KEYOUTWAIT22。 JNB ,WAIT21 INC 7BH MOV A,7BH CJNE A,08H,KEYOUT11KEYOUT11: JC KEYOUT1 MOV 7BH,00HKEYOUT1: RET；WAIT21: LCALL DISP ；鍵釋放等待時(shí)顯示用 AJMP WAIT22；END附錄二　參考文獻(xiàn)①《新編實(shí)用數(shù)字化測(cè)量技術(shù)》，沙占友，國(guó)防工業(yè)出版社，1998。②《單片機(jī)基礎(chǔ)》，李廣第，朱月秀，王秀山，北京航空航天大學(xué)出版社，2001。③《單片機(jī)課程設(shè)計(jì)實(shí)例知道》，李光飛，北京航空航天大學(xué)出版社，2004。④《電子技術(shù)》，房建東、高勝利，內(nèi)蒙古大學(xué)出版社，2004。⑤《單片機(jī)實(shí)用系統(tǒng)設(shè)計(jì)技術(shù)》，房小翠、王金鳳，國(guó)防工業(yè)出版社，1999。⑥《電子創(chuàng)新設(shè)計(jì)與實(shí)踐》，王松武，于鑫，武思軍，國(guó)防工業(yè)出版社，2005。⑦ 　模擬電子技術(shù)幫學(xué)網(wǎng)。⑧《A/D、D/A轉(zhuǎn)換器接口技術(shù)與實(shí)用電路》，楊振江，西安電子科技大學(xué)出版社。⑨《新編實(shí)用數(shù)字化測(cè)量技術(shù)》，沙占友，國(guó)防工業(yè)出版社，1998。⑩ Digital Voltmeter MkIII, The easytouse digital voltmeter with a doitall LCD readout.附錄三　文獻(xiàn)翻譯The principle of digitaltoanalogue conversion The principle digitaltoanalogue conversion of mould conversion is that the digital quantity of be dispersed changes the simulated quantity that changes to join , realizes device or the circuit of this function to be called as digitaltoanalogue changeover circuit , is usually called as the DAC or converter of D/A ( Digital Analog Converter ). It can count and have no right to have right to count. If we know that divide frequently, claim have right number is its each number have a coefficient, if the 4 in the 45 of decimal numeral is expressed for 410, , 5 is of 51, the coefficient of 4 is 10, and the coefficient of 5 is 1, digitaltoanalogue conversion from certain kind meaning on say is the number with the several conversion of binary system of decimal system. The most original DAC circuit from below some parts of form: Refer to voltage source , sue for peace operational amplifier and right produce circuit network, register and clock standard produce circuit, the role of register is the digital signal that will be inputed deposit in its export end, when it changes the voltage change of input will not draw its output instability. Clock standard produces circuit, is corresponding mainly to refer to voltage source, it guarantees to input the phase property of digital signal, is will not be disorderly in transition , the wow and flutter of clock standard ( jitter ) can make the noise of high frequency. Its data right coefficient of binary system produce , what rely on is that resistance and CD form are 16 bit, 16. So with 16 resistances in correspondence with 16 in each. Reference voltage source passes every current of resistance in proper order with the current with each datain add right sue for peace can reach simulated signal. This is bit DAC. The place of the difference of 1 bit and much bit is , much bit is to carry out potential through internal accurate resistance network to pare , and changes eventually to imitate signal, benefit lies in high development to follow ability and high development scope, but the precision of resistance have decided the precision of much bit converter, to reach the conversion precision of 24 bits, the requirement for resistance is as high as , will be larger than this value even the hinderance value fluctuation that its hot noise and the resistance of ideal form , what much bit system now adopt extensively is that R2 R laddershaped resistance network can reduce for the precision requirement of resistance , but will not also reach 24 bits even the conversion precision as this and ideal state that resistance reaches , 23 bits has been simple for limit much bit systematic advantage to lie in design , but gets the precision that made in resistance, cost is also high. The principle of single bit: The method of support mathematics operation is inserted in the pulse code signal of CD ( PCM ) into sampling point, it is that 18 times passes sampling to insert into 7 sampling points, it is these to insert the sampling a little and original signal that entered to pass through integral circuit to carry out parison, value big is 1 surely, value Xiao De is 0 surely, former PCM signal has bee the data that has only 1 and 0 to flow, it is more sparse that 1 representative datas flow out more dense, 0 representative datas to flow, this is pulse density modulation signal ( PDM ) , the low clear wave filter and 1 that pulse density modulation signal forms via a switch capacity network change , is high voltage signal, 0 changes , then pass through cascade integral for low voltage signal, last conversion is simulated signal. The advantage of 1 bit lies in that conversion precision does not get system in resistance, conversion precision can exceed 24 bits , has also low cost, but design passes the circuit difficulty of sampling and noise plastic greatly. Beca