【正文】 . To do this, set up the Zregister the same way as described in the section regarding Page Erase. Then set the PGWRT and SPMEN bits in the SPMCR Register and execute the SPM instruction within four cycles. The R1:R0 Register contents are ignored. The use of the Zregister for 32word (64byte) page write is shown in Figure 5.Figure 5. Writing a Page to FlashThe SPMEN bit can be polled to find out when the CPU is ready for further page updates. The update procedure can also be interrupt controlled. See the section on interrupts below for more information.（4）、The RWW Section Busy Flag When performing a Page Erase or Page Write operation on the RWW section, the RWWSB Flag is set by hardware, indicating that the section is inaccessible. The RWWSB Flag should be cleared in software when the SPM operation is pleted. This is done by setting the RWWSRE and SPMEN bits in the SPMCR Register, followed by an SPM instruction within four cycles. Alternatively, the flag is automatically cleared by starting to load the Page Buffers. The RWWSB Flag can be used by other parts of the application to check the RWW section’s current accessibility. Refer to the devices’ datasheet for more details.Note that the contents of the Zregister and the R1:R0 Registers are ignored when using the RWWSRE function.Note that if the RWW section accessed without reenabling it after an erase or write operation, all addresses in the RRW section read 0xFFFF. This applies both when reading the Flash using LPM and if performing calls or jumps into the RWW section. The consequence of performing a jump into the RWW section without enabling it will therefore be that the program code “0xFFFF” is executed, eventually leading to that the program counter “falls” through the code space until it meets the first executable first executable code would in that case be encountered on the first address of the NRWW section.（5）The Boot Lock Bits The application and Boot Loader section can be protected on different levels. There are four levels of protection for both sections. A short description of the modes follows.ModeBitsDescription111Full read/write access210No write access300No write access and no read access (data or interrupt execution)from the other section.401No read access (data or interrupt execution) from the other section.Table 1. Boot Lock ModesNote that once programmed (cleared), it is impossible to unprogram the bits again without using serial or parallel programming. For instance, to implement an application that is to be updated once, set Boot Lock mode 1 on the Application section, and mode 4 on the Boot Loader section. This prevents the application from accessing the Boot Loader, while giving the Boot Loader full access to update the application section. Once updated, the Boot Loader would set mode 3 on the Application section, thus blocking all further access To program the Boot Lock bits, load the R0 Register with the correct bits, set the BLBSET and SPMEN bits in the SPMCR Register and execute the SPM instruction within four cycles. The contents of the Zregister are ignored. Using the LPM instruction instead of the SPM instruction will read the bits.Interrupt ConsiderationsIt is possible to use interrupts while writing to the RWW section, but the software must prevent any other access to the RWW section. In other words, interrupt service routines to be executed while updating the RWW section must be placed in the NRWW section,including the Interrupt Vectors.Using the IVSEL bit in the GICR Register, the application can be used to implement two separate Interrupt Vector tables. One in the Application section, and one in the Boot Loader section to be used when updating the RWW section. This enables the application to continue critical processes, ., safety monitoring, during to the devices’ data sheet for more details on interrupts and the IVSEL Flag.If the secondary Interrupt Vectors are not used, the interrupts must be disabled during RWW section updates.The SPM InterruptOn all devices supporting Selfprogramming, except the ATmega163 and ATmega323 devices, it is possible to control the Flash update operations using interrupts. Setting the SPMIE bit in the SPMCR Register will enable the SPM ready interrupt. This can be used to indicate when the current SPM operation is finished.EEPROM Conflicts Note that all write operations to the EEPROM must be finished before executing the SPM instruction and vice versa. Write/erase of the Flash and EEPROM cannot occur simultaneously.Typical Update ProceduresTwo mon update procedures are shown in Figure 6. The flowchart to the left describes a ReadModifyWrite operation used to update small parts of the Flash, ., a constant string contained in Flash memory. The flowchart to the right describes a Page Write operation used to write whole pages without reading previous contents, ., write data received from an UART.Figure 6. Typical Update FlowchartsⅣ、Boot Loader ExampleThe Boot Loader software presented in this application note uses the AVR Open Source Programmer (AVROSP) as the user interface. The example application implements functions to read or update the Flash and EEPROM memories on the target device. It is also possible to read and update the Lock bits and read the Fuse bits of the device.Ⅴ、AVRProg CompatibilityAVRProg patibility relies upon device codes, which are not defined for all devices. The file contains the defined device codes, but some are not yet implemented in the AVRProg executable. In this case, use a code from a device with the same memory sizes. AVROSP, relies on signature bytes only, and accepts all devices with selfprogrammingcapabilities.Ⅵ、ProtocolThe protocol used by the Boot Loader program is a subset of the protocol defined for list of supported mands is shown in Table 2 on page 8. All mands start with a single letter. The programmer returns 13d (carriage return) or the request