【導(dǎo)讀】SCMisnotonlyfar

　　

【正文】 the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) in the slice, arranges blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three abovementioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. 8051 onechip puter have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate twoway mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction, but four function of pass way these selfsame. Expand among the system of memory outside having slice, four ports these may serve as accurate twoway mouth of I/O in mon use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off。 P0 mouth is a twoway bus, send the introduction of 8 low addresses and data/export in timesharing The circuit of 8051 onechip puters and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rationally, and will inspire to designing the peripheral logical circuit of onechip puter to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in mon with each other. P0 mouth is different from other mouths。 its output grade draws the resistance supremely. When using it as the mouth in mon use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should write 1 to a latch first. Everyone with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate twoway mouth too, used as I/O in mon use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two states, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate, can draw the pin to the high level fast 。 When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw the resistance on needn39。t answer and thinning. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, and make FET end. Relatively about 20,000 ohms because of the load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1? P3 mouth one multifunctional port, mouth getting many than P1 it have “and” 3 doors and 4 buffers. Two parts these, make her besides accurate twoway function with P1 mouth just, can also use the second function of every pin, “and” door 3 functions one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W =at 1 o39。clock, output Q end signal。 Act as Q =at 1 o39。clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn39。t have software that set up P3 mouth in advance. It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location (the location or the byte ) to visit to P3 mouth /at not lasting lining, there are inside hardware latch Qs = operation principle of P3 mouth is similar to P1 mouth. Output grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 onechip puters as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drainsource resistance is it urge to open a way, do not need to have the resistance of drawing outerly. Mouths are all accurate twoway mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 onechip puter, port can only offer milliamp ere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an onechip puter. Its main function is t