【正文】 vations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage(VPP) during Flash programming, for parts that require 12volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Status of External Pins During Idle and Power Down ModesmodeProgram memoryALE^psenPort0 Port1Port2Port3idleinternal11datadatadataDataIdleExternal11floatDatadataDataPower downInternal00DataDataDataDataPower downExternal 00floatdataDatadataPower Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash：The at89s52 is normally shipped with the onchip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a highvoltage (12volt) or a lowvoltage (VCC) program enable signal. The low voltage programming mode provides a convenient way to program the at89s52 inside the user’s system, while the highvoltage programming mode is patible with conventional third party Flash or EPROM programmers. The at89s52 is shipped with either the highvoltage or lowvoltage programming mode enabled. The respective topside marking and device signature codes are listed in the following table.Vpp=12vVpp=5vTopside markat89s52xxxxyywwat89s52xxxx5yywwsignature(030H)=1EH(031H)=51H(032H)=FFH(030H)=1EH(031H)=51H(032H)=05HThe at89s52 code memory array is programmed bytebybyte in either programming mode. To program any nonblank byte in the onchip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming the at89s52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the at89s52, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct bination of control signals.4. Raise EA/VPP to 12V for the highvoltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The bytewrite cycle is selftimed and typically takes no more than ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The at89s52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the plement of the written datum on . Once the write cycle has been pleted, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. is pulled low after ALE goes high during programmin