【正文】 trickle charger for VCC1, and seven additional bytes of scratchpad memory. （ 1）、 OPERATION The main elements of the Serial Timekeeper are shown in Figure 1: shift register, control logic, oscillator,real time clock, and RAM. DS1302 BLOCK DIAGRAM Figure 1 30 （ 2）、 SIGNAL DESCRIPTIONS ① VCC1： VCC1 provides low power operation in single supply and battery operated systems as well as low power battery backup. In systems using the trickle charger, the rechargeable energy source is connected to this pin. ② VCC2 ： Vcc2 is the primary power supply pin in a dual supply configuration. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power. ③ The DS1302 will operate from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + , VCC2 will power the DS1302. When VCC2 is less than VCC1, VCC1 will power the DS1302. ④ SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface. ⑤ I/O (Data Input/Output) – The I/O pin is the bidirectional data pin for the 3wire interface. ⑥ RST (Reset) – The reset signal must be asserted high during a read or a write. ⑦ X1, X2 ： Connections for a standard kHz quartz crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6 pF. （ 3）、 COMMAND BYTE The mand byte is shown in Figure 2. Each data transfer is initiated by a mand byte. The MSB (Bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 through 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The mand byte is always input starting with the LSB (bit 0). ADDRESS/COMMAND BYTE Figure 2 31 （ 4）、 RESET AND CLOCK CONTROL All data transfers are initiated by driving the RST input high. The RST input serves two functions. First, RST turns on the control logic which allows access to the shift register for the address/mand sequence. Second, the RST signal provides a method of terminating either single byte or multiple byte data transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the RST input is low all data transfer terminates and the I/O pin goes to a high impedance state. Data transfer is illustrated in Figure 3. At power–up, RST must be a logic 0 until VCC volts. Also SCLK must be at a logic 0 when RST is driven to a logic 1 state. DATA TRANSFER SUMMARY Figure 3 （ 5）、 DATA INPUT Following the eight SCLK cycles that input a write mand byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0. （ 6）、 DATA OUTPUT Following the eight SCLK cycles that input a read mand byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the mand byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as RST remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri–stated upon each rising edge of SCLK. Data is output starting with bit 0. （ 7）、 BURST MODE Burst mode may be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/mand bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0. When writing to the clock registers in 32 the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not. （ 8）、 CLOCK/CALENDAR The clock/calendar is contained in seven write/read registers as shown in Figure 4. Data contained in the clock/ calendar registers is in binary coded decimal format (BCD). REGISTER ADDRESS/DEFINITION Figure 4： （ 9）、 CLOCK HALT FLAG 33 Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1302 is placed into a low–power standby mode with a current drain of less than 100 nanoamps. When this bit is written to logic 0, the clock will start. The initial power on state is not defined. （ 10）、 AMPM/1224 MODE Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode, bit 5 is the second 10hour bit (20 – 23 hours). （ 11）、 WRITE PROTECT BIT Bit 7 of the control register is the writeprotect bit. The first seven bits (bits 0 – 6) are forced to 0 and will always read a 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write protect bit prevents a write operation to any other register. The initial power on state is not defined. Therefore the WP bit should be cleared before attempting to write to the device. （ 12）、 TRICKLE CHARGE REGISTER This register controls the trickle charge characteristics of the DS1302. The simplified schematic of Figure 5 shows the basic ponents of the trickle charger.