【導讀】在脈寬調(diào)制中使用高分辨率計數(shù)器來產(chǎn)生方波，并且可以通過調(diào)整。方波的占空比來對模擬信號電平進行編碼。PWM通常使用在開關電源（switching. power）和電機控制中。StellarisPWM模塊由3個PWM發(fā)生器模塊1個控制模塊組成。發(fā)生器模塊包含1個定時器，2個PWM比較器，PWM信號發(fā)生器，死區(qū)發(fā)生器和中斷/ADC-觸發(fā)選擇器。這些PWM發(fā)生模塊的輸出信號在傳遞到器件管。3個發(fā)生器模塊也可產(chǎn)生3相反相器橋所需的完整6. 在遞減計數(shù)模式中，定時器從裝載值開始計數(shù)，計數(shù)到零時又返回到裝。載值并繼續(xù)遞減計數(shù)。這些限定脈沖在生成PWM信號的過程中使用。則丟棄第二個PWM信號，并在第一個PWM信號基礎上產(chǎn)生兩個PWM信號。一個輸出PWM信號為帶上升沿延遲的輸入信號，延遲時間可編程。具有全局復位功能，該功能可同時復位PWM發(fā)生器中的任何或全部計數(shù)器。調(diào)試器引發(fā)的控制器中止。用戶可以將PWM發(fā)生器配置為在停止條件期間停止計數(shù)。到管腳的PWM信號進行修改。同樣地，故障控制也能夠禁能所有的PWM信號。

　　

【正文】 nting while the processoris halted by the debugger. The timer resumes counting when the processor resumes execution. 32Bit RealTime Clock Timer Mode In RealTime Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registersare configured as a 32bit upcounter. When RTC mode is selected for the first time, the counter isloaded with a value of . All subsequent load values must be written to the GPTM TimerAMatch (GPTMTAMATCHR) register by the input clock on an even CCP input is required to be KHz in RTC mode. The clock signalis then divided down to a 1 Hz rate and is passed along to the input of the 32bit counter. When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from itspreloaded value of . When the current count value matches the preloaded value in theGPTMTAMATCHR register, it rolls over to a value of and continues counting untileither a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTMIMR, theGPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flagsare cleared by writing the RTCCINT bit in the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze ifthe RTCEN bit is set in GPTMCTL. 16Bit Timer Operating Modes The GPTM is placed into global 16bit mode by writing a value of 0x4 to the GPTM Configuration(GPTMCFG) register. This section describes each of the GPTM 16bit modes ofoperation. TimerA and TimerB have identical modes, so a single description is given using an n toreference both. 16Bit OneShot/Periodic Timer Mode In 16bit oneshot and periodic timer modes, the timer is configured as a 16bit downcounter withan optional 8bit prescaler that effectively extends the counting range of the timer to 24 bits. Theselection of oneshot or periodic mode is determined by the value written to the TnMR field of theGPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down fromits preloaded value. Once the 0x0000 state is reached, the timer reloads its start value froGPTMTnILR and GPTMTnPR on the next cycle. If configured to be a oneshot timer, the timer stopscounting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, itcontinues addition to reloading the count value, the timer generates interrupts and triggers when it reachesthe 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it iscleared by writing the GPTMICR register. If the timeout interrupt is enabled in GPTMIMR, the GPTMalso sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The ADC trigger isenabled by setting the TnOTE bit in the GPTMCTL software reloads the GPTMTAILR register while the counter is running, the counter loads the newvalue on the next clock cycle and continues counting from the new the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processoris halted by the debugger. The timer resumes counting when the processor resumes execution. 16Bit Input Edge Count Mode In Edge Count mode, the timer is configured as a downcounter capable of capturing three typesof events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bitof the GPTMTnMR register must be set to 0. The type of edge that in theGPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events thatmust be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabledfor event capture. Each input event on the CCP pin decrements the counter by 1 until the event countmatches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in theGPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTMautomatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached,all further events are ignored until TnEN is reenabled by software. 16Bit Input Edge Time ModeIn Edge Time mode, the timer is configured as a freerunning downcounter initialized to the valueloaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture ofeither rising or falling edges, but not both. The timer is placed into Edge Time mode by setting theTnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMTnILR register. 16Bit PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as adowncounter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWMfrequency and period are synchronous events and therefore guaranteed to be glitch free. PWMmode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to0x0, and the TnMR field to software writes the TnEN bit in the GPTMCTL register, the counter begins counting downuntil it reaches the 0x0000 state. On the next counte